Stmicroelectronics (rousset) Sas

Other

Stmicroelectronics S.r.l.

Stmicroelectronics S.a.

Université´ D'aix-Marseille

France Universite D'aix-marseille

Romain Laffont

Jean-Michel Mirabel

Rachid Bouchakour

Arnaud Regnier

Pascal Masson

Richard P Fournel

Philippe Candelier

Philippe Gendrier

Olivier Pizzuto

Pierre Canet

Juliano Razafindramora

Virginie Bidal

A non-volatile memory point including a floating gate placed above a semiconductor substrate, the floating gate comprising active portions insulated from the substrate by thin insulating layers, and inactive portions insulated from the substrate by thick insulating layers that do not conduct electrons, the active portions being principally P-type doped, and the inactive portions comprising at least one N-type doped area forming a portion of a PN junction.

Non-volatile reprogrammable memory

The present invention relates to a floating-gate MOS transistor, comprising drain and source regions implanted into a silicon substrate, a channel extending between the drain and source regions, a tunnel oxide, a floating gate, a gate oxide and a control gate extending according to a determined gate length. According to the present invention, the control gate comprises a small gate and a large gate arranged side by side and separated by an electrically insulating material. Application to the production of memory cells without access transistor, and to the implementation of an erase-program method with reduced electrical stress for the tunnel oxide.

Floating-gate MOS transistor with double control gate

The invention relates to a production process for a flash memory from a semi-conductor substrate fitted with at least two adjacent rows of precursor stacks of floating gate transistors, the precursor stacks being at least partially covered by a protective resin and being separated by a formation zone for a source line. The process includes forming a trench in the formation zone for the source line by an attack of this zone and of the protective resin. The result of the attack step includes a deposit of residue from the resin below the precursor stacks. The residue deposit is removed. A source line is implanted in the formation zone below the precursor stacks. This process enables the time needed for erasing the memory to be reduced.

Manufacturing process for a flash memory and flash memory thus produced

A memory cell in an EEPROM includes a floating gate transistor that includes a first conducting terminal and a control gate. A method of controlling the memory cell includes setting a state of the memory cell by simultaneously applying voltage pulses of opposite polarities respectively to the first conducting terminal and to the control gate. The voltage pulses including a first portion having a first slope and a second portion having a second slope, wherein the second slope is based upon the polarities of the voltage pulses. The method allows the amplitude of the voltage pulses to be reduced.

Method of controlling an electronic non-volatile memory and associated device

Growing community of inventors

Marseilles, France

Romain Laffont