Stmicroelectronics (Grenoble 2) Sas

Stmicroelectronics Gmbh

Stmicroelectronics (Alps) Sas

Stmicroelectronics (Grenoble) Sas

Stmicroelectronics S.r.l.

Stmicroelectronics S.a.

Stmicroelectronics (Rousset) Sas

Stmicroelectronics (Research & Development) Limited

Stmicroelectronics (Malta) Ltd

Romain Coffy

Jean-Michel Riviere

Remi Brechignac

Karine Saxod

Fabien Quercia

Alexandre Coullomb

Jerome Teysseyre

Yonggang Jin

Eric Saugier

Denis Farison

Laurent Schwartz

Rémi Brechignac

Patrick Laurent

Julien Vittu

Gil Provent

Julien Pruvost

Jacky Seiller

Laurent Marechal

Yvon Imbs

Emmanuelle Vigier-Blanc

Luc Petit

Hk Looi

Olivier Le-Briz

Kenneth Fonk

Jacques Chavade

Younes Boutaleb

Florian Perminjat

Norbert Chevrier

Stuart Robertson

Georg Kimmich

Angelo Crobu

Dominique Marais

Yann Guillou

Jean-François Sauty

Joseph Hannan

Carlo Cognetti De Martiis

A non-conductive encapsulation cover is mounted on a support face of a support substrate to delimit, with the support substrate, an internal housing. An integrated circuit chip is mounted to the support substrate within the internal housing. A metal pattern is mounted to an internal wall of the non-conductive encapsulation cover in a position facing the support face. At least two U-shaped metal wires are provided within the internal housing, located to a side of the integrated circuit chip, and fixed at one end to the metallic pattern and at another end to the support face.

Electronics unit with integrated metallic pattern

An electronic circuit includes an upper substrate and a lower substrate. An electronic integrated circuit chip is positioned between the upper and lower substrates. The chip includes contact elements coupled to the upper substrate. A first region made of a first material is arranged between the chip and a heat transfer area crossing the lower substrate. A second region filled with a second material couples the lower and upper substrates and laterally surrounds the first region. The first material has a thermal conductivity greater than a thermal conductivity of the second material.

Electronic circuit

A package includes an upper level mounted to a lower level. The upper level includes a stack formed by insulating layers and conductive elements and includes a first conductive track of an antenna. A plastic element rests on the stack. A first cavity is defined in the plastic element. A second conductive track of the antenna is located on a wall of the plastic element (for example, in or adjacent to the first cavity). A second cavity is also defined in the plastic element surrounding the first cavity. A third conductive track of the antenna is located on a wall of the plastic element (for example, in the second cavity). A third cavity is delimited between the upper and lower levels and an integrated circuit chip is mounted within the third cavity and electrically connected to the antenna.

Antenna package

An electronic device includes a first electronic component and a second electronic. Each electronic component includes a carrier substrate having a back side and a front side, an electronic chip including an integrated optical element, an overmolded transparent block encapsulating the electronic chip above the carrier substrate, and electrical connections between the electronic chip and electrical contacts of the carrier substrate. An overmolded grid encapsulates and holds the first and second electronic components. The grid is configured so that sides of the first and second electronic components are at least partially exposed.

Electronic device comprising optical electronic components and fabricating process

An optoelectronic device includes an emitter of light rays and a receiver of light rays. The emitter is encapsulated in a transparent block. An opaque conductive layer is applied to a top surface and a side surface of the transparent block. The receiver is mounted to the opaque conductive layer at the top surface. An electrical connection is made between the receiver and the opaque conductive layer. A conductive strip is also mounted to the side surface of the transparent block and isolated from the opaque conductive layer. A further electrical connection is made between the receiver and the conductive strip.

Optoelectronic device

An optoelectronic element is located in a package. The package includes a first optical block and a second optical block that are attached to each other by a bonding layer. One of the first and second optical blocks is attached to lateral walls of the package by glue. The material of the bonding layer is configured to induce less stress to the first and second optical blocks than the glue.

An integrated circuit chip includes a front face having an electrical connection pad. An overmolded encapsulation block encapsulates the integrated circuit chip and includes a front layer at least partially covering a front face of the integrated circuit chip. A through-hole the encapsulation block is located above the electrical connection pad of the integrated circuit chip. A wall of the through-hole is covered with an inner metal layer that is joined to the front pad of the integrated circuit chip. A front metal layer covers a local zone of the front face of the front layer, with the front metal layer being joined to the inner metal layer to form an electrical connection. The inner metal layer and the front metal layer are attached or anchored to activated additive particles that are included in the material of the encapsulation block.

Electronic device including electrical connections on an encapsulation block

An electronic chip supports an optical device and electric connection zones. An insulating coating coats the electronic chip, covers the electric connection zones and exposes the optical device. An optical plugging element is at least partly fastened onto a first face of the insulating coating and is optically coupled to the optical device. Vias pass through the insulating coating from its first face to a second face opposite to the first face. Inner walls of the vias support electrically conductive paths connected to the electric connection zones of the electronic chip by electrically conductive tracks arranged on the first face of the insulating coating. The electrically conductive paths of the vias further have ends protruding onto the second face of the insulating coating.

Optical package of an integrated circuit

A device includes a substrate and an optoelectronic chip buried in the substrate. The substrate may include an opening above a first optical transduction region of the first optoelectronic chip and above a second optical transduction region of a second optoelectronic chip.

Optical transmission/reception circuit

A first integrated circuit chip is assembled to a second integrated circuit chip with a back-to-back surface relationship. The back surfaces of the integrated circuit chips are attached to each other using one or more of an adhesive, solder or molecular bonding. The back surface of at least one the integrated circuit chips is processed to include at least one of a trench, a cavity or a saw cut.

Protection of integrated circuits

A cover for an electronic circuit package, including: a body having an opening extending therethrough; a first element located in the opening and having a surface continuing planar or rounded shapes of a surface of the cover; and a second element of connection of the first element to the body.

Cover for an electronic circuit package

Growing community of inventors

Voiron, France

Romain Coffy