Qimonda North America Corporation

Infineon Technologies Ag

Mitsubishi Semiconductor America, Inc.

Qimonda Ag

Qimonda North Amercia Corp.

Mitsubishi Semiconductor of America, Inc.

Rom-Shen Kao

Vickie L Gibbs

Peter Mayer

Jong-Hoon Oh

Jason Pratt Parrish

Nicholas Heath

Mehrdad Hamadani

In one embodiment, an integrated circuit comprises circuitry for performing bus inversion. The circuitry is operable to configure the integrated circuit to implement one of a plurality of bus inversion schemes each of which the integrated circuit is capable of performing. The circuitry is also operable to process data input to and output from the integrated circuit based on the bus inversion scheme for which the integrated circuit is configured.

Multi-mode bus inversion method and apparatus

An integrated circuit includes an array of memory cells and a first circuit. The array includes word lines. Each word line is coupled to a plurality of memory cells. The first circuit is configured to refresh memory cells along a first number of word lines in response to a refresh command. The first number of word lines is based on a sensed temperature.

Integrated circuit including memory refreshed based on temperature

Embodiments of the invention may generally provide techniques that allow mapping of memory devices in a multi-chip package (MCP) to memory segments of an address space. For some embodiments, a multi-bit device ID, which corresponds to a memory segment to which that device is mapped, is loaded for each memory device. Higher order address bits are then compared to the device IDs assigned to each device. An internally generated chip select line is asserted for a device having a match between the address bits and its device ID.

Method of flexible memory segment assignment using a single chip select

Embodiments of the invention may generally provide techniques that allow a single externally supplied chip select signal to be used to independently select a plurality of devices in a multi-chip package (MCP). For some embodiments, higher order address bits are compared to device IDs assigned to each device. An internally generated chip select line is asserted for a device having a match between the address bits and its device ID.

Method of simple chip select for memory subsystems

A data path in a memory device is configured by selecting a data path configuration configured to at least partially maintain data bit order between the memory device and a chip carrier. The memory data path is arranged based on the data path configuration for memory operations where maintaining data bit order between the memory device and the chip carrier is required.

Configurable memory data path

Embodiments of the invention generally provide methods, systems, and articles of manufacture for selecting a data bus inversion (DBI) mode of operation. A comparison circuit of a device may receive multiple packets of data to be transmitted to another device over a bus connecting the devices. The comparison circuit may compare the multiple packets of data and select a DBI mode of operation that conserves power and reduces noise on the bus.

Self-adapted bus inversion

Embodiments of the invention provide a method and apparatus for initializing a computer system, wherein the computer system includes a processor, a volatile memory, and a non-volatile memory. In one embodiment, the method includes, when the computer system is initialized, automatically copying initialization code stored in the non-volatile memory to the volatile memory, wherein circuitry in the volatile memory automatically creates the copy, and executing, by the processor, the copy of the initialization code from the volatile memory.

System method for performing a direct memory access for automatically copying initialization boot code in a new memory architecture

Embodiments of the invention provide a method and apparatus for accessing a non-volatile memory controller and a volatile memory via a shared interface. In one embodiment, the method includes selecting one of the non-volatile memory controller and the volatile memory via shared control signals of the shared interface, wherein the shared control signals are issued to the non-volatile memory controller and the volatile memory. The method also includes issuing commands to the selected one of the non-volatile memory controller and the volatile memory via the shared control signals.

Shared interface for components in an embedded system

Embodiments of the invention provide a method, devices, and system for accessing data in a nonvolatile memory device via a volatile memory device. In one embodiment, the method includes configuring a size and a base address of an overlay window within an address space of the volatile memory device. The overlay window includes a range of memory addresses. The method also includes receiving an access command via a volatile memory interface of the volatile memory device and using the access command to access a memory array of the volatile memory device if an address of the access command is outside of the overlay window. The method further includes using the access command to access the nonvolatile memory device via a nonvolatile memory interface of the volatile memory device if the address of the access command is within the overlay window.

Method for accessing a non-volatile memory via a volatile memory interface

A method for reading data is provided. The method includes generating two or more pulses from a first clock signal by which the data to be read is received, using each generated pulse to latch data received at a corresponding time, and detecting a first time region during which the data is received. The method also includes using the detected first time region to determine a second time region during which the data may be read using the second clock signal and reading the data using a second clock signal during the second time region.

Methods of DDR receiver read re-synchronization

A multimedia data encoding and decoding system capable of handling various types of data arranged in variable-size blocks. Frames of image, graphics and text data are supplied to a frame buffer. In response to an encoding command from a CPU, an MPEG encoder compresses the data from the frame buffer in accordance with the MPEG compression algorithm, and outputs to a texture buffer a variable-size data block that corresponds to the frame portion to be displayed. The size of the data block is set by the CPU, and may vary from one macroblock to, e.g., 22.times.16 macroblocks (one frame for MPEG-1). An MPEG decoder reads the variable-size data block from the texture buffer, decompresses and supplies it to a graphics engine that manipulates various type of data to create a picture to be displayed at a video monitor.

MPEG encoding and decoding system for multimedia applications

An address generator provided on an error control chip of an optical disk storage for addressing a plurality of working buffers accessed by a CPU, an optical disk drive (ODD), and encoder/decoder circuitry during error correction operations. The address generator comprises a loading address generator that produces an adop address signal to provide linear buffer access for the CPU and ODD when data are supplied from and to the CPU and ODD for encoding and decoding. A processing address generator produces an adex address signal that provides interleaving and random buffer access for the encoder/decoder circuitry during data encoding and decoding operations. A buffer rotation control circuit produces address and data bus control signals to provide the rotation of the buffers between the CPU, ODD, and encoder/decoder circuitry in various encoding and decoding cycles to support a pipeline error control arrangement.

Address generator for error control system

A circuit for determining locations of the errors that occur during data storage tests each possible error location using an error location polynomial. Accumulating registers of a set of multiplier accumulators are loaded with the components of the error location polynomial at the start of each 120-byte word to be tested. The output signals of the accumulating registers are transferred to an XOR checksum circuit. If the output of the XOR checksum circuit is determined to be zero, the current byte of the tested word is considered to be an error location. An external clock signal corresponding to the consecutive bytes to be tested saves the outputs of the unary multipliers for multiplying by the Galois field elements .alpha..sup.123 -.alpha..sup.131, through a feedback loop to the multiplier accumulating registers.

Method and apparatus for determining error location

In an error correction system, which incorporates Cyclic Redundancy Check (CRC) and a Reed-Solomon (RS) code, original data are encoded simultaneously by CRC and RS encoders. The CRC encoder processes the words 0-9 of the original data to form CRC check bytes, which become the last bytes in words 6, 7, 8 and 9. The RS encoder processes 104-byte words 0-9 of original data to form 16 redundant RS bytes per word. The words 0-5 are simultaneously supplied from a codeword memory to CRC and RS encoders. The redundant RS bytes generated by the RS encoder are sent back to the codeword memory, while the CRC encoder saves the CRC check bytes in local registers. For words 6-9 the RS encoder processes the bytes of original data and stops processing before the CRC bytes. It then temporarily saves the generated data in the codeword memory and waits for the CRC encoder to finish encoding. Once the CRC encoder completes, the CRC bytes corresponding to the words 6-9 are processed by the RS. encoder to finish each set of the redundant RS bytes.

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Durham, NC, United States of America

Rom-Shen Kao