Ncr Corporation

Rolfe D Armstrong

George B Gillow

Chiman R Patel

Victor F Cole

Jon M Corcoran

Charles R Lang, Jr

Dennis A Walsh

A fault tolerant data processing system includes a pair of processors for simultaneously executing commands for processing data, a memory, and a data transmission bus between the processors and the memory voer which the processors may fetch data from and write data to the memory. A comparison circuit is included between the processors for comparing the data fetched and written by the processors. A rollback module is responsive to the comparison circuit for rolling back the operation of the processors to the beginning of a presently executing command in the event of a miscomparison by the comparison circuit.

Virtual command rollback in a fault tolerant data processing system

A jump return stack is provided in a data processor having a plurality of control registers including a fetch control register and an execution control register. The jump return stack comprises a memory stack, an address register, and a counter-register interposed between the memory stack and the control registers of the data processor. The counter-register is always made to store the latest entry into the memory stack, that is the top of the stack, such that the latest entry into the stack is immediately available to the control registers of the data processor thereby eliminating a memory access to the stack.

Jump return stack

Diagnostic circuitry for use with the processor of a data processing system. The diagnostic circuitry includes a control register execution log for receiving control store addresses from a control register associated with an 'EXECUTE+1' stage. A log pointer addresses the log when control store addresses are written into or read from the log. Test registers connected to the log and log pointer provide control store addresses and decrementing log addresses when the contents of the log are examined. One of the test registers is also used to hold a control store address for comparison with control store addresses of executing microinstructions, and when a match occurs, to generate a SYNC signal.

Diagnostic circuitry in a data processor

Parity prediction circuitry for use with a multifunction register. The parity prediction circuitry includes a parity prediction circuit associated with each function of the register. A selecting multiplexer selects the parity prediction circuit that will provide a predicted parity bit at the output of the parity prediction circuitry, with the selection controlled by the same control signals that select the function of the register. The parity prediction circuits associated with COUNT UP and COUNT DOWN functions also include a multiplexer, with this multiplexer having data inputs connected in a predetermined fashion to signals having a value of either logic level '1' or logic level '0'. This multiplexer has control inputs connected to the data outputs of the register and has a data output selected by the control inputs in order to provide a signal indicating whether the predicted parity is to change from the previous predicted parity.

Parity prediction circuitry for a multifunction register

A mask generator for use in a digital computer receives input signals defining the beginning and the end addresses of the inhibiting bits of the mask. The mask generator includes decoder circuits for receiving the input signals and a look-ahead carry circuit whose output signals represent the mask.

Selectively operable mask generator

An electrically configurable decoder including selectively configurable combinations of a plurality of basic decode circuits. The electrically configurable decoder includes a plurality of mode selection inputs, a plurality of address inputs, a plurality of logic level definition inputs, and a plurality of disable inputs. Various combinations of decoding functions are provided by the electrically configurable decoder in response to the mode selection inputs. A plurality of selection circuits selectively decodes various ones of the address inputs and mode selection inputs to produce signals which are applied to decode inputs and enable inputs of the basic decoder circuits. A logical 'one' applied to a first one of the logic level definition inputs causes 'high' and 'low' voltage levels produced at the outputs of a first one of the basic decoder circuits to represent logical 'ones' and 'zeroes,' respectively. A disable signal applied to one of the disable inputs of the electrically configurable decoder causes the outputs of the first basic decoder circuits to assume logical 'zero' levels as determined by the first logic level definition input.

Electrically configurable high-low decoder

A one bit multifunction arithmetic and logic circuit is implemented with a pair of inverters, four two input NOR gates, three two-input OR/NOR gates, and two three-input NOR gates. Each of the inverters has four wire OR-able outputs, two of which are inverting and two of which are non-inverting. One input of each of the four two-input NOR gates is coupled to a respective one of four control inputs of the arithmetic and logic circuit; the other input thereof is coupled to respective ones of four wire ORed combinations of the outputs of the first and second inverters. Various outputs of the first, second, third, and fourth two-input NOR gates are wire ORed together. A first one of the three-input NOR gates is responsive to the generate signal, a carry signal, and the wired OR output of the first and second two-input NOR gates. The second three-input NOR gate is responsive to the propagate signal, a carry signal, and the 'output disable' input. The first outputs of the first and second three-input NOR gates are wire ORed together to produce a first 'sum' output; the second output of the first and second three-input NOR gates are wire ORed together to produce a second sum output which may be used as a wire OR-able 'zero result' indicator signal.

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Escondido, CA, United States of America

Rolfe D Armstrong