Infineon Technologies Ag

Infineon Technologies Dresden Gmbh

Qimonda Ag

Infineon Technologies Austria Ag

Infineon Technologies Dresden Gmbh & Co . Kg

International Business Machines Corporation

Other

Rolf Weis

Franz Hirler

Marko Lemke

Stefan Tegen

Gerald Deboy

Till Schloesser

Armin Willmeroth

Ahmed Mahmoud

Andreas Peter Meiser

Thomas Happ

Martin Feldtkeller

Hans Weber

Matthias Stecher

Ralf Rudolf

Christoph Noelscher

Marco Mueller

Anton Mauder

Markus Zundel

Helmut Horst Tews

Peter Irsigler

Wolfgang Bergner

Anthony Sanders

Dirk Manger

Ulrike Gruening-von Schwerin

Marc Strasser

Richard Hensch

Wolfgang Mueller

Richard Anthony Conti

Jochen C Beintner

Wolfgang Granig

Henning Feick

Michael Treu

Hans-Peter Moll

Richard Johannes Luyken

Markus Schmitt

Martin Popp

Andreas Knorr

Martin Bartels

Joachim Nuetzel

Detlef Weber

Franz Stueckler

Katarzyna Kowalik-Seidl

Peng-Fei Wang

Ulrike Gruening Von Schwerin

Thomas Wahls

Ramachandra Divakaruni

Richard Stephan Wise

Peter Baars

Harry Hedler

Martin Schrems

Johnathan E Faltermeier

Byeong Yeol Kim

David M Dobuzinsky

Larry Alan Nesbit

Stephan Kudelka

Hiroyuki Akatsu

Heinz Hoenigschmid

Uwe Wahl

Johannes Baumgartl

Martin Henning Vielemeyer

Christoph Ludwig

Siddhartha Panda

Hermann Gruber

Michael Herfurth

Michael Kund

Roland Irsigler

Munir D Naeem

Stephan Wege

Klaus Muemmler

Herwig Wappis

Bernd Goebel

Peter Moll

Uwe Schroeder

Thomas Gross

Adrian Finney

Irene Lennox McStay

Knut Stahrenberg

Florian Schnabel

Matthias Kroenke

Norbert Thyssen

Odo Wunnicke

Markus Rochel

Alessandro Ferrara

Steffen Meyer

Frank Ludwig

Wolfgang Henke

Johann Harter

Hannes Luyken

Burkhard Ludwig

Ulrike Grüning Von Schwerin

Klaus Krischan

Kimberly Wilson

Phillip Stopford

David Mark Dobuzinksy

Martin Vielemeyer

Josef Deichler

Christoph Kubasch

GillYong Lee

A method for producing a protection device and a protection device are disclosed. The method includes: forming a first diode arrangement including at least one first diode and at least one second diode connected in anti-series between a first circuit node and a second circuit node of the first diode arrangement; forming a second diode arrangement including at least one first diode and at least one second diode connected in anti-series between a first circuit node and a second circuit node of the second diode arrangement; and connecting the second circuit node of the first diode arrangement and the second circuit node of the second diode arrangement.

Protection device with space saving layout

A transistor arrangement is disclosed. The transistor arrangement includes a first transistor device and a second transistor device. The first transistor device and the second transistor device are connected in series and integrated in a common semiconductor body. The first transistor device is a lateral superjunction transistor device and is integrated in a first device region of the semiconductor body. The second transistor device is a lateral transistor device and is integrated in at least one second device region of the semiconductor body. The at least one second device region is spaced apart from the first device region.

Transistor arrangement with a lateral superjunction transistor device

According to an embodiment of a semiconductor device, the device includes: a transistor or diode device formed in a semiconductor substrate; an insulating material at least partially covering a lateral drift zone of the transistor or diode device or a termination region; and a fill pattern disposed over the lateral drift zone or termination region, the fill pattern having a variable density that follows equipotential lines of an electric field distribution expected between the fill pattern at a surface of the lateral drift zone or termination region during operation of the semiconductor device. Corresponding methods of producing the semiconductor device are also described.

Fill pattern for power transistor and diode devices

The disclosure relates to a semiconductor die with a transistor device, which has a channel region formed in a semiconductor body, a gate region aside the channel region, for controlling a channel formation, a drift region formed in the semiconductor body, and a field electrode in a field electrode trench, which extends from a frontside of the semiconductor body vertically into the drift region, wherein an insulating layer is formed on the frontside of the semiconductor body and a frontside metallization is formed on the insulating layer, and wherein a capacitor electrode is formed in the insulating layer, which is conductively connected to at least a portion of the field electrode.

Semiconductor die with a power device and method of manufacturing the same

A transistor device includes a semiconductor body having a substantially planar main surface, a source region extending to the main surface and having a first conductivity type, a body region extending to the main surface and having a second conductivity type, a drain region extending to the main surface and having the first conductivity type, a drift region having the first conductivity type, and a gate electrode arranged on the main surface laterally between the source and drain regions and electrically insulated from the semiconductor body by an insulation structure. The insulation structure includes a gate dielectric arranged on the main surface and a shallow trench arranged in the drift region and filled with electrically insulating material. The shallow trench has at least partly a wedge shape and the electrically insulating material has an upper surface that is substantially planar and extends substantially parallel to the main surface.

Transistor device

A semiconductor device includes a layer stack with first semiconductor layers and second semiconductor layers of opposite doping types arranged alternatingly. A first semiconductor region of a first semiconductor device adjoins the first semiconductor layers, and has a first end arranged in a first region of the first semiconductor device and extends from the first end into a second region of the first semiconductor device. Second semiconductor regions of the first semiconductor device adjoin at least one of the second semiconductor layers. A third semiconductor region of the first semiconductor device adjoins the first semiconductor layers. The first semiconductor region extends from the first region into the second region and is spaced apart from the third semiconductor region. The second semiconductor regions are arranged between, and spaced apart from, the third and first semiconductor regions. An average doping concentration along a shortest path between the first and third semiconductor regions in at least one of the first or second semiconductor layers in the first region differs from an average doping concentration along a shortest path between the first and third semiconductor regions of the same layer in the second region.

Semiconductor device having a high breakdown voltage

A semiconductor device includes a layer stack with first and second semiconductor layers of complementary doping types are arranged alternatingly between first and second surfaces of the layer stack. A first semiconductor region adjoins the first semiconductor layers and has a first end arranged in a first device region and extends from the first end into a second device region. Second semiconductor regions adjoin at least one of the second semiconductor layers. A third semiconductor region adjoins the first semiconductor layers. The first semiconductor region extends from the first device region into the second device region and is spaced apart from the third semiconductor region. The second semiconductor regions are arranged between, and spaced apart from, the third and first semiconductor regions. A fourth semiconductor region adjoins the first semiconductor layers, is spaced apart from the first semiconductor region, and is arranged in the first device region between the first end of the first semiconductor region and the third semiconductor region.

A method includes forming a layer stack with a plurality of first layers of a first doping type and a plurality of second layers of a second doping type complementary to the first doping type on top of a carrier. Forming the layer stack includes forming a plurality of epitaxial layers on the carrier. Forming each of the plurality of epitaxial layers includes depositing a layer of semiconductor material, forming at least two first implantation regions of one of a first type or a second type at different vertical positions of the respective layer of semiconductor material, and forming at least one second implantation region of a type that is complementary to the type of the first implantation regions, the first implantation regions and the second implantation regions being arranged alternatingly.

Semiconductor device and method for producing a semiconductor device

An electronic circuit is disclosed. The electronic circuit includes: a first transistor device integrated in an inner region of a first semiconductor body; a level shifter integrated in a level shifter region of the first semiconductor body, the level shifter region located in an edge region surrounding the inner region of the semiconductor body; and a drive circuit integrated in a drive circuit region in the edge region of the first semiconductor body, the drive circuit configured to receive a first input signal from a first input and drive the first transistor device based on the first input signal, the drive circuit region arranged closer to the inner region than the level shifter region.

Electronic circuit with a transistor device, a level shifter and a drive circuit

A semiconductor device includes a layer stack with a plurality of first semiconductor layers of a first doping type and a plurality of second semiconductor layers of a second doping type complementary to the first doping type. A first semiconductor region of a first semiconductor device adjoins the first semiconductor layers. Each second semiconductor region of the first semiconductor device adjoins at least one of the second semiconductor layers, and is spaced apart from the first semiconductor region. A third semiconductor layer adjoins the layer stack and each first semiconductor region and each second semiconductor region. The third semiconductor layer includes a first region arranged between the first semiconductor region and the second semiconductor region in a first direction. A third semiconductor region of the first or the second doping type extends from a first surface of the third semiconductor layer into the first region.

Semiconductor device and method of producing the same

A transistor arrangement includes: a layer stack with first and second semiconductor layers of complementary first and second doping types; a first source region of a first transistor device adjoining the first semiconductor layers; a first drain region of the first transistor device adjoining the second semiconductor layers and spaced apart from the first source region; gate regions of the first transistor device, each gate region adjoining at least one second semiconductor layer, being arranged between the first source region and the first drain region, and being spaced apart from the first source region and the first drain region; a third semiconductor layer adjoining the layer stack and each of the first source region, first drain region, and each gate region; and active regions of a second transistor device integrated in the third semiconductor layer in a second region spaced apart from a first region of the third semiconductor layer.

Superjunction transistor arrangement and method of producing thereof

An electronic circuit is disclosed. The electronic circuit includes: a first transistor device integrated in an inner region of a first semiconductor body; and a first drive circuit integrated in a first drive circuit region of the semiconductor body. The first drive circuit is configured to be connected to a level shifter and to drive a second transistor device. The first drive circuit region is located in an edge region surrounding the inner region of the semiconductor body.

Electronic circuit with a transistor device and a level shifter

A transistor arrangement and a method are disclosed. The transistor arrangement includes: a plurality of first semiconductor regions of a first doping type and a plurality of second semiconductor regions of a second doping type, the first semiconductor regions and the second semiconductor regions being arranged alternatingly in a vertical direction of a semiconductor body; a source region adjoining the plurality of first semiconductor regions; a drain region adjoining the plurality of second semiconductor regions and arranged spaced apart from the source region in a first lateral direction; and a plurality of gate regions each of which adjoins at least one of the plurality of second semiconductor regions and is arranged between the source region and the drain region. At least one of the first and semiconductor regions, but less than each of the first and second semiconductor regions has a doping dose that varies in the first lateral direction.

Lateral superjunction transistor device and method for producing thereof

A method includes: forming first and second trenches in a semiconductor body; forming a first material layer on the semiconductor body in the first and second trenches such that a first residual trench remains in the first trench and a second residual trench remains in the second trench; removing the first material from the second trench; and forming a second material layer on the first material layer in the first residual trench and on the semiconductor body in the second trench. The first material layer includes dopants of a first doping type and the second material layer includes dopants of a second doping type. The method further includes diffusing dopants from the first material layer in the first trench into the semiconductor body to form a first doped region, and from the second material layer in the second trench into the semiconductor body to form a second doped region.

Method for forming complementary doped semiconductor regions in a semiconductor body

A method for forming a battery element includes etching trenches into a substrate and crystal orientation dependent etching of the trenches. Further, the method includes forming solid state battery structures within the trenches.

Method for forming a battery element, a battery element and a battery

Growing community of inventors

Dresden, Germany

Rolf Weis