Csr Technology Inc.

Fingerprint Cards Ab

Anacatum Design Ab

Zoran Corporation

Fingerprint Cards Anacatum IP Ab

Anatacum Design Ab

Rolf Sundblad

Robert Hägglund

Christer Jansson

Staffan Gustafsson

Emil Hjalmarson

Staffan Holmbring

Emil Hjalmarsson

Karl Lundahl

David Carling

Klaas-Jan De Langen

Peter Almers

Nicholas Weiner

Benjamin Willcocks

Gordon A Wilson

Erik Säll

Allan Olsson

Graham R Leach

A method of controlling operation of a field-powered biometric device comprising biometric acquisition circuitry, processing circuitry controllable to transition between a first functional state having a first power consumption and a second functional state having a second power consumption lower than the first power consumption, and power management circuitry. The method comprises the steps of monitoring, by the power management circuitry, a property indicative of a supply voltage to the processing circuitry; controlling, when the monitored property indicates that the supply voltage has fallen to a first threshold voltage, the processing circuitry to transition from the first functional state to the second functional state; and controlling, when the monitored property indicates that the supply voltage has increased to a second threshold voltage higher than the first threshold voltage, the processing circuitry to transition from the second functional state to the first functional state.

Field-powered biometric device, and method of controlling a field-powered biometric device

There is provided a capacitive fingerprint sensing device for sensing a fingerprint pattern of a finger, said capacitive fingerprint sensing device comprising: a protective top layer to be touched by said finger; a first metal layer comprising a two-dimensional array of sensing structures arranged underneath said top layer; a second metal layer, arranged underneath said first metal layer, comprising a plurality of conductive structures a dielectric layer arranged between the first and second metal layers to electrically insulate the first metal layer from the second metal layer, the dielectric layer comprising a low-k material; and readout circuitry arranged underneath said second metal layer and coupled to each of the electrically conductive sensing structures by means of via connections to receive a sensing signal indicative of a distance between said finger and said sensing structure. There is also provided a method for manufacturing such a device.

Fingerprint sensing device and method for manufacturing a fingerprint sensing device

A fingerprint sensing system comprising a device connection interface including a device reference potential input, a sensing arrangement, and sensing reference potential providing circuitry. The sensing arrangement includes multiple sensing structures and read-out circuitry connected to each of the sensing structures. The sensing reference potential providing circuitry provides a sensing reference potential to the sensing arrangement in the form of a sensing reference signal alternating between a first sensing reference potential and a second sensing reference potential, and comprises a first capacitor; a second capacitor; charging circuitry; and switching circuitry for alternatingly switching the sensing reference potential providing circuitry between a first state in which the first capacitor and the second capacitor are connected in parallel to the charging circuitry; and a second state in which the first capacitor and the second capacitor, when charged, are connected in series between the device reference potential input and the sensing arrangement.

Fingerprint sensing system with sensing reference potential providing circuitry

A cognitive signal converter adapted to produce a digital output signal based on an analog input signal comprises an analog-to-digital converter (ADC) and a cognitive network. The ADC is adapted to produce a digital converted signal based on the analog input signal, a sample clock signal and a process clock signal by sampling the analog input signal in accordance with the sample clock signal and quantizing each analog input signal sample based on the process clock signal. The cognitive network is adapted to receive the digital converted signal of the ADC, control at least one of the sample clock signal and the process clock signal based on the received digital converted signal and one or more characteristics of the analog signal source, and produce the digital output signal based on the received digital converted signal. Corresponding integrated circuit, electronic device and method are also disclosed.

Cognitive signal converter

A time-interleaved analog-to-digital converter for conversion of L analog input signals to L corresponding digital output signals comprises an array of N (N&#x3e;L) constituent analog-to-digital converters each having an analog input and a digital output and each adapted to digitize an analog input sample, and a controller adapted to (for each of the L analog input signals indexed by i=1, 2, . . . , L) select a number N, of constituent analog-to-digital converters from the array of N constituent analog-to-digital converters (wherein N&#x2267;1 and &#x3a3;N&#x2266;N), and cause each sample of the analog input signal to be digitized in a respective one of the selected N, constituent analog-to-digital converters. The analog-to-digital converter also comprises a multiplexer adapted to (for each of the L analog input signals) multiplex the digitized samples of each of the selected Ni constituent analog-to-digital converters to produce the digital output signal.

Configurable time-interleaved analog-to-digital converter

A method of operating a time-interleaved analog-to-digital converter for conversion of an analog input signal to a digital output signal having a sample rate R comprises, for each of at least some activations of an array of constituent analog-to-digital converters, defining first and second sets of the constituent analog-to-digital converters, feeding the analog input of each analog-to-digital converter of the first set with a reference value for imperfection measurements and clocking each analog-to-digital converter of the first set with one of the timing signals, feeding the analog input of each of analog-to-digital converter of the second set with the analog input signal for generation of an intermediate constituent digital output signal at the digital output and clocking each analog-to-digital converter of the second set with one of the timing signals, wherein no timing signal is used to clock two or more of analog-to-digital converters of the second set.

Estimation of imperfections of a time-interleaved analog-to-digital converter

A time-interleaved analog-to-digital converter for conversion of an analog input signal to a digital output signal having a sample rate R comprises an array of N constituent analog-to-digital converters that operate based on an analog-to-digital converter operation clock to provide the digital output signal, N sample-and-hold units connected to the input of a respective constituent analog-to-digital converter that operate based on a respective one of M of timing signals, wherein no timing signal is used to clock two or more of the sample-and-hold units, one or more digital output processing units that provide a sample of the digital output of a constituent analog-to-digital converter as a sample of the digital output signal based on the respective one of the M timing signals, and a timing circuit that generates the analog-to-digital converter operation clock signal, each timing signal having a period of M/R, wherein M is less or equal to N.

Efficient time-interleaved analog-to-digital converter

A PLL circuit () for generating a pixel-clock signal based on a hsync signal. The PLL circuit comprises a phase-frequency detector arranged to receive the hsync signal and a frequency divided pixel-clock signal, and generate up and down signals based on the hsync signal and the frequency-divided pixel-clock signal. A charge pump () is arranged to generate an output signal based on the up and down signals and a loop filter () is arranged to generate a frequency-control signal based on the output signal of the charge pump (). Furthermore, a VCO () is arranged to generate an oscillating signal and adjust the frequency of the oscillating signal in response to the frequency-control signal. The VCO () is adapted to have a tuning range with a center frequency which is larger than or equal to 4 GHz. A programmable first frequency divider () is arranged to generate the pixel-clock signal by frequency division of the oscillating signal, and a programmable second frequency divider () is arranged to generate the frequency divided pixel-clock signal by frequency division of the pixel-clock signal.

Phase-locked loop

A track and hold circuit that includes a switch device and a capacitive hold device. The track and hold circuit includes a track-voltage generating device adapted to generate a control voltage based on a signal on an input terminal of the switch device and supply the control voltage to the switch device during track phases of the track and hold circuit. The control voltage provides a channel charge, which is the same for each track phase, in the switch device.

Track and hold circuit

A track and hold circuit () comprising a switch device () and a capacitive hold device (). The track and hold circuit () comprises a track-voltage generating device () adapted to generate a control voltage based on a signal on an input terminal of the switch device () and supply the control voltage to the switch device () during track phases of the track and hold circuit (). The control voltage provides a channel charge, which is the same for each track phase, in the switch device ().

An arrangement is disclosed for offset compensation of a time-interleaved analog-to-digital converter, having a plurality of computing channels and being adapted to convert a signal from an analog domain to a digital domain. The arrangement comprises the time-interleaved analog-to-digital converter, an analog offset estimation and compensation unit adapted to estimate a mean offset for the plurality of computing channels, a digital offset estimation and compensation unit adapted to estimate a residual computing channel specific offset for each of the plurality of computing channels, and offset compensation means. The offset compensation means are adapted to perform offset compensation in the analog domain of each of the plurality of channels based on the estimated mean offset in the analog domain, and to perform offset compensation in the digital domain of each of the plurality of channels based on respective residual computing channel specific offset.

Methods of and arrangements for offset compensation of an analog-to-digital converter

A gain circuit comprises a main amplification unit and a first refresh unit. The main amplification unit comprises an amplifier, a first capacitor connected between a first input terminal of the gain circuit and a first input terminal of the amplifier, and a second capacitor connected between the first input terminal of the amplifier and a first output terminal of the amplifier. The first refresh unit comprises a first capacitor connected with a first terminal of the first capacitor to a common node of the first refresh unit, and a second capacitor connected with a first terminal of the second capacitor to the common node of the first refresh unit. The common node of the first refresh circuit is arranged to be supplied with a reference voltage (V, V) during a first phase of a refresh interval and connected to the first input terminal of the amplifier during a second phase of the refresh interval.

Gain circuit

A latch circuit () comprising a first input device () in a first branch () and a second input device () in a second branch (). The latch circuit comprises a first estimator unit () adapted to generate a first estimate of a current generated by the first input device () and a second estimator unit () adapted to generate a second estimate of a current generated by the second input device (). The latch circuit further comprises a control-voltage unit () operatively connected to the first and the second estimator unit (). The control-voltage unit is adapted to generate a control voltage based on a sum of the first estimate and the second estimate. Further, the latch circuit () comprises a first and a second voltage-controlled current unit () adapted to generate currents at least based on the control voltage. The first voltage-controlled current unit () is operatively connected to the first branch (). The second voltage-controlled current unit () is operatively connected to the second branch (). A method for compensation for common-mode variations in the latch circuit () is also disclosed.

Growing community of inventors

Ljungsbro, Sweden

Rolf Sundblad