Bts Broadcast Television Systems Gmbh

Thomson Licensing S.a.

Rolf Schiffmann

Berthold Eiberger

Rolf Hedtke

Michael Philipps

Henrikus Antonius Vaanholt

Peter Ries

An improved utilization of the storage space on a helical scan recording and/or reproduction apparatus in particular according to the D6 format. In the case of a data transfer rate in which the apparatus recording rate corresponds to an integer multiple of the data transfer rate of data signals to be recorded, the recording is effected in a manner dependent on the ratio of apparatus recording rate to the data transfer rate by a corresponding first portion of the volume of data being written to first data frames () and, after corresponding rewinding, by the corresponding second portion of the volume of data subsequently being written to second data frames ().

Interleave mode for helical scan recording

A monostable multivibrator having a time constant that is approximately one-quarter of the period of a pulse signal supplied to its input is used for frequency doubling of a 50% keying ratio input pulse signal. The output signals of the multivibrator are low-pass filtered and supplied to inputs of a different amplifier operating as a difference integrator by virtue of a capacitance connected between its output and its inverting input. This output is utilized to modify the time constant when the period of the input pulse sequence becomes more than about four times the time constant of the multivibrator, thus keeping the keying ratio of the output signals at 50% over a wide range of variation of the frequency of the usually symmetrically input pulse sequence. The multivibrator is connected so as to be triggered by both rising and falling flanks of the input pulses. Both ECL and TTL embodiments are shown.

Circuit apparatus for generating a symmetrical pulse sequence of

To the phase locked loop for controlling the oscillator that regenerates a bit-rate clock signal from a data signal by means of a phase comparison circuit followed by a low pass filter, the output of which controls the oscillator frequency, a digital frequency comparison circuit is provided for assuring that the oscillator frequency will be brought into the capture range of the phase locked loop. The output of the digital frequency comparison circuit is converted from digital to analog form for being used in combination with the low pass filter output to control the oscillator. Frequency and phase control signals are applied to opposite electrodes of a variable capacitance diode in the frequency determining circuit of the oscillator. In order to improve the operation the frequency comparison circuit, delayed and undelayed oscillator output clock signals are sampled by transitions of the data signal for respectively incrementing or decrementing a counter, the state of which is then converted into an anlog signal for contributing to the control of the oscillator. The data signal also is provided in delayed and undelayed forms, and these are combined in an exclusive-OR gate, the output of which is used both in the phase comparison circuit and in the sampling portion the frequency comparison circuit. That portion of the frequency comparison circuit controls a pair of monoflops through D-flipflops so as to provide the necessary incrementing or decrementing pulses for the counter.

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Mainz, Germany

Rolf Schiffmann