Infineon Technologies Ag

Rolf-Peter Vollertsen

Martin Schrems

Georg Tempel

Joachim Hoepfner

A chip includes a logic circuit which has a plurality of transistors and is configured to carry out a logical data processing function, the transistors being operated in a first direction when carrying out the data processing function, and a readout circuit which is configured to control the logic circuit in such a manner that the transistors are operated in a second direction opposite the first direction and is configured to determine an identification of the logic circuit on the basis of an output from the logic circuit when operating the transistors in the second direction.

Chip and method for identifying a chip

An apparatus and method is described for measuring a local surface temperature of a semiconductor device under stress. The apparatus includes a substrate, and a reference MOSFET. The reference MOSFET may be disposed closely adjacent to the semiconductor device under stress. A local surface temperature of the semiconductor device under stress may be measured using the reference MOSFET, which is not under stress. The local surface temperature of the semiconductor device under stress may be determined as a function of drain current values of the reference MOSFET measured before applying stress to the semiconductor device and while the semiconductor device is under stress.

Apparatus and method for measuring local surface temperature of semiconductor device

A semiconductor circuit element for reducing undesirable charging effects for a connection element of test structures for semiconductor circuits is disclosed. A surface of a semiconductor circuit element has interconnect structures that are electrically insulated from the remainder of the surface of the semiconductor circuit element, where exclusively the interconnect structures are connected to semiconductor circuit elements arranged downstream.

Structured semiconductor element for reducing charging effects

A method for reducing a capacitance formed on a silicon substrate includes the step of introducing hydrogen atoms into a portion of said surface to increase the dielectric constant of such portion of the surface increasing the effective thickness of the dielectric material and hence reducing said capacitance. The method includes the step of forming the silicon dioxide layer with a thickness greater than two nanometers. The step of introducing hydrogen includes forming hydrogen atoms in the surface with concentrations of 10 atoms per cubic centimeter, or greater. In one embodiment the hydrogen atoms are introduced by baking in hydrogen at a temperature of 950&deg; C. to 1100&deg; C. and pressure greater than 100 Torr. A trench capacitor DRAM cell is provided wherein the hydrogen provides a passivation layer to increase the effective capacitance around a collar region and thereby reduce unwanted transistor action.

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Grasbrunn, Germany

Rolf-Peter Vollertsen