Sony Deutschland Gmbh

Rolf Nöthlings

Jens Wildhagen

Taiwa Okanobu

Dietmar Schill

Carsten Merkle

Jens Wildnagen

In an automatic gain control unit, the gain of a voltage-controlled amplifier (VCA) () is regulated with a closed-loop control circuit. The time constant of the control circuit is varied dependent on the magnitude () of the VCA output signal. As long as the magnitude () of the VCA output signal is small, the gain is slowly adjusted. In case the magnitude () of the VCA becomes so large that saturation of the analog-digital converter () might occur, the time constant of the control circuit is decreased, in order to allow for a quick adjustment of the amplifier's gain.

Automatic gain control

The bandwidth of a first variable IF filter () for a neighbour channel suppression of a currently received channel, which first variable IF filter () is arranged in a first reception path of a broadcast receiver additionally comprising at least one second reception path is controlled by obtaining at least one first quality signal corresponding to a received broadcast signal on basis of a first filtering of the received and eventually pre-processed broadcast signal with said first variable IF filter () set to a predetermined bandwidth, obtaining at least one second quality signal corresponding to said received broadcast signal on basis of at least one second filtering of the received and eventually pre-processed broadcast signal with a second variable IF filter () arranged in said at least one second reception path with a bandwidth different to the first variable IF filter () bandwidth and/or with a different filter characteristic, and controlling the bandwidth of the first variable IF filter () on basis of a the at least one first quality signal and the at least one second quality signal.

Digital FM bandwidth control

A digital filter realization is proposed that consists of only one multiplier, i. e. which operates with a higher clock rate and changes coefficient at the multiplier each clock cycle, but in which the clock rate of the multiplier is reduced in comparison to prior art filters by considering equal filter coefficients, e. g. based on the symmetry of FIR filter coefficients. According to the present invention preferably the samples belonging to equal filter coefficients are added in advance in order to reduce the number of multiplications, which concludes in a reduced clock rate for the filter, a reduced needed calculation power, and therefore a reduced power consumption.

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Stuttgart, Germany

Rolf Nöthlings