Texas Instruments Corporation

Mediatek Singapore Pte. Ltd.

Rolf Lagerquist

Hugh Thomas Mair

Kenneth James Maggio

Gordon Gammie

William Robert Krenik

Alice Wang

Sumanth Katte Gururajarao

Steve Clynes

David Barry Scott

Hao Chen

Uming U Ko

Clive D Bittlestone

Dharin Nayeshbhai Shah

Girishankar Gurumurthy

Uming Ko

Lee-Kee Yong

Dennis V Hahn

Senthil Kumar Sundaramoorthy

Patrick G O'Farrell

Nitin Kumar Singh

Rajarshee P Bharadwaj

Various examples with respect to dual threshold clock control are described. A method involves sensing an input voltage of a processing circuit with a first mechanism and a second mechanism different from the first mechanism. The method also involves regulating a first droop of the input voltage using the first mechanism. The method further involves regulating a subsequent droop of the input voltage after the first droop using the second mechanism.

Method and apparatus of dual threshold clock control

A method of detecting and preventing over current induced system failure is provided. An OC protect controller monitors a CPU total power consumption based on received CPU activity information. In response to the monitoring, if the CPU power consumption is over a threshold, then the OC protect controller outputs a frequency dithering control signal to reduce the CPU clock frequency such that the CPU does not reach an OC limit. The OC protect controller also outputs a PLL frequency control signal to reduce the PLL clock frequency to improve system efficiency.

Fast and Autonomous mechanism for CPU OC protection

A method is provided that includes performing a free placement of a system design comprising a plurality of power domains, wherein the power domains are not constrained to physical regions, assigning a physical region to each of the power domains based on the free placement of cells in the power domains, performing a soft cluster placement of the system design with each power domain and corresponding physical region defined as a soft cluster, refining at least one physical region based on the soft cluster placement, redefining cells in at least one power domain based on the soft cluster placement of the cells and the corresponding physical region, and performing a hard cluster placement of the system design with each power domain and corresponding physical region defined as a hard cluster to generate final power domains.

Method and system for adaptive physical design

System and method for reducing power-on transient current magnitude on distributed header switches. A preferred embodiment comprises a distributed header switch coupling a circuit to a power supply, the distributed header switch comprising a linear sequence of combination switches, each combination switches containing a pre-charge switch and a header switch. A first-pass involves sequentially turning on each of the pre-charge switches, which enables a voltage level at the distributed header switch to approach that of a final voltage level and a second-pass involves sequentially turning on each of the header switches. Since the voltage level at the distributed header switches is close to the final voltage level, a resulting transient current is small in magnitude.

System and method for reducing power-on-transient current magnitude

An integrated circuit. The integrated circuit comprises an area having a layout aligned in rows. Each row is definable by a pair of row boundaries. The integrated circuit also comprises a plurality of cells, comprising a first set of cells. Each cell in the first set of cells spans at least two rows and comprises a PMOS transistor having a source/drain region that spans across one of the row boundaries and an NMOS transistor having a source/drain region that spans across one of the row boundaries.

Performance and area scalable cell architecture technology

System and method for providing power with a large on-current and small off-current to circuitry in an integrated circuit. A preferred embodiment comprises a switch for providing power to circuits in an integrated circuit made from a PMOS transistor and an NMOS transistor coupled in parallel. Each transistor's gate terminal is coupled to a separate control signal line. The PMOS transistor provides current to the circuits at high voltage supply levels while the NMOS transistor provides current to the circuits at low voltage supply levels, wherein the size of the PMOS and NMOS transistor can be changed during design to meet power requirements. Depending upon power requirements, multiple PMOS and NMOS transistors may be used. The combination of PMOS and NMOS transistors permit the use of limited fabrication processes wherein transistor widths can be limited.

Integrated header switch with low-leakage PMOS and high-leakage NMOS transistors

System and method for reducing power-on transient current magnitude

A method of expanding data to a high-speed serial video link in such a way that it is invisible to existing receivers and such that auxiliary data, i.e. audio data, can be transmitted without any knowledge of the capabilities of the display to receive the auxiliary data.

Method of expanding high-speed serial video data providing compatibility with a class of DVI receivers

An encoding scheme simplifies the TMDS encoding algorithm described in the DVI 1.0 specification while retaining compatibility with most existing DVI receivers. The generation of the Transition Control bit has been removed; and although the INV bit has a similar function to the DC bit in the DVI 1.0 standard, the algorithm for deriving it is very different. No attempt is made to maintain a DC balance on the cable. Instead, the INV bit is set to a '1' for the purpose of removing 'rogue' character sequences; otherwise it is always set to a &lsquo;0&rsquo;.

Method of encoding video data for serial transmission

A predriver for a differential pair having a reduce voltage swing is disclosed having fast switching speed and low power consumption. The predriver includes a p-type MOS transistor, and a first and second n-type MOS transistor. The source of the p-type MOS couples to the first power supply rail. The gate of the first n-type MOS transistor couples to the gate of the p-type MOS transistor to form an input. The drain of the first n-type MOS transistor couples to the drain of the p-type MOS transistor to form an output. The drain of the second n-type MOS transistor couples to the source of the first n-type MOS transistor. The source of the second n-type MOS transistor couples to ground. The gate of the second n-type MOS transistor couples to the output. The presence of the second n-type MOS transistor alters the voltage swing of the predriver to be from the threshold voltage level to the full power supply voltage, substantially reducing the current or power consumption.

Reduced voltage swing digital differential driver

A circuit for controlling the slew rate in the stator coils of a polyphase, dc motor is provided. The circuit includes a first steady state control circuitry (12), a low side commutation circuitry (60), a second steady state control circuitry (62), and a high side commutation circuitry (64). The first steady state control circuitry (12) regulates the current through an A-coil (14) and a C-coil (18) after a high side commutation. The A-coil (14) couples to a voltage source through an HSDA (22) at one end and couples to the C-coil (18) through a center tap at the other end. The C-coil (18) couples to an LSDC (24) at its other end during this state. The low side commutation circuitry (60) performs a low side commutation by controlling the current slew rate of the C-coil (18) and a B-coil (16) as the current in the C-coil (18) is reduced to zero and the current in the B-coil (16) is increased from zero to a steady state level. The B-coil (16) couples to the center tap on one end and to an LSDB (52) at its other end. The second steady state control circuitry (62) regulates the current through the A-coil (14) and a B-coil (16) after a low side commutation. The high side commutation circuitry (64) performs a high side commutation by controlling the current slew rate of the C-coil (18) and the A-coil (14) as the current in the A-coil (14) is reduced to zero and the current in the C-coil (18) is increased from zero to a steady state level. The C-coil (18) couples between an HSDC (66) and the center tap during this state.

Circuitry and method for controllable slew rate

A shock sensor circuitry (26) is provided for processing an input signal generated by a shock sensor (28) in response to the shock sensor (28) detecting a force or shock. The shock sensor circuitry (26) includes a leakage tolerant input amplifier (38) for receiving the input signal, and any leakage currents that may also be provided, and amplifying the input signal to generate an amplified input signal. The leakage tolerant input amplifier (38) provides an ac gain of ten and a dc gain of zero. The shock sensor circuitry (26) also includes a filter and amplification circuit and a window comparator. The filter and amplification circuit filters the amplified input signal and amplifies select frequencies of the amplified input signal to generate a summed signal that is provided to the window comparator and compared to a reference value. The window comparator includes an upper comparator (58), a lower comparator (60), and an output circuit (62) to generate a shock sensor circuitry output signal that indicates whether a shock or force was received at a magnitude greater than the reference value.

Shock sensor circuitry and method for amplifying an input signal

A current feedback amplifier (12) is provided for controlling a stator winding phase current in a polyphase stator winding, such as a three-phase stator winding (10), of a polyphase direct current motor. The current amplifier (12) includes a first stage current feedback amplifier C (27) and a second stage current feedback amplifier (100) coupled through a switch (101). The first stage current feedback amplifier C (27) detects a stator winding phase current I.sub.AB flowing through a C-coil (15) of the three-phase stator winding (10) and generates an equalized sense current I.sub.senseT in response that is related to I.sub.AB. The equalized sense current I.sub.senseT is generated using a phase trim FET (31) and an adjustable phase trim FET (32). The second stage current feedback amplifier (100) receives I.sub.senseT from the first stage current feedback amplifier C (27) and generates a control signal. This may be done by comparing I.sub.senseT to an amplitude adjusted reference current I.sub.refT. The amplitude adjusted reference current I.sub.refT is generated using an amplitude trim FET (81) and an adjustable amplitude trim FET (82). The second stage current feedback amplifier (100) provides the control signal to a driver circuit for controlling the stator winding phase current. The second stage current feedback amplifier (100) may sequentially or commutatively couple to other first stage current sense amplifiers, such as a first stage current feedback amplifier B (30) or a first stage current feedback amplifier A (28), to control other stator winding phase currents to generate equalized, amplitude adjusted stator winding phase currents.

Current feedback amplifier having trimcircuitry and method for

A motor driver circuit (12) for providing drive signals to stator coils of a polyphase dc motor (10) includes a plurality of current paths, each connected between a supply voltage and a reference potential. Each current path includes two driver transistors (14,20, 16,22, 18,24), a node (A, B, C) of each of the stator coils being connectable between the driver transistors in respective current flow paths. A commutator (26) is connected to operate the driver transistors in a sequence in which drive currents are delivered for application in a predetermined sequence to the stator coils. A plurality of sensing transistors (32) are connected to produce a mirror current which mirrors a mirrored current in an associated driver transistor (20) in a respective current flow path. Circuitry (26) is provided which is responsive to the mirror currents of the sensing transistors to control the amplitudes of the currents in the associated driver transistor in a respective current flow path. At least one trim transistor (51-55) is connected in parallel with a respective one of the sensing transistors (50), and a programmable circuit (48) is connected to selectively activate the at least one trim transistor to adjust the amplitudes of the mirrored currents in the current flow path with which the sensing transistor with which the at least one trim transistor is associated.

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Richardson, TX, United States of America

Rolf Lagerquist