Advanced Micro Devices Corporation

Atmel Corporation

Atmel Germany Gmbh

Rolf Jaehne

Wolfram Kluge

Eric Sachse

Tilo Ferchland

Frank Poegel

Thorsten Riedel

Lutz Dathe

Sascha Beyer

Andreas Huschka

Torsten Bacher

In one embodiment, a method includes receiving a radio frequency (RF) signal; synchronizing the received RF signal with a preamble to determine a time base; determining a first energy value of the received RF signal by averaging received signal strength indication (RSSI) values of the received RF signal over a first period of time; determining a second energy value of the received RF signal over a second period of time; determining a difference value between the first energy value and the second energy value; comparing the difference value with a predetermined energy threshold value; determining a quality value of the received RF signal; comparing the quality value of the received RF signal with a predetermined quality threshold value; and, if the difference value exceeds the predetermined energy threshold value or the quality value is below the predetermined quality threshold value, then erasing the time base.

Receiver and method for the reception of a node by a receiver in a wireless network

A receiver and method for operating a receiver, in particular of a radio network, is provided, whereby the receiver includes circuit blocks in a receive path for detecting a preamble of a received signal, and a controller for controlling a receive mode. Whereby at least some of the circuit blocks are designed to be capable of being turned on for a turn-on duration and turned off for a turn-off duration. Whereby, the controller is configured to alternately turn on at least some of the circuit blocks for the turn-on duration and off for the turn-off duration during the receive mode, wherein the turn-off duration is shorter than the preamble. Whereby, the controller is configured to compare a first measured value measured in the receive path to a first threshold, and the controller is configured to change the turn-on duration and/or the turn-off duration on the basis of a result of the comparison with the first threshold, and whereby the controller is configured to compare a second measured value to a second threshold in order to detect a valid signal of the preamble and, on the basis of a result of the comparison with the second threshold, to terminate the turn-off and to drive the portion of the circuit blocks into a turned-on state for a synchronization by means of the preamble.

Receiver and method for operating a receiver

A frequency modulator is provided for generating an output signal with a frequency that is a function of a modulation signal, wherein the modulation signal can assume N&#x2267;2 different discrete modulation values, and a predetermined frequency value of the output signal is associated with each modulation value, containing: a) a closed phase locked loop with a loop filter for providing a first control voltage, with a voltage controlled oscillator for generating the output signal, and with a switchable frequency divider for deriving a frequency-divided signal, and b) a modulation unit that is designed to provide, at a first output, values of a divisor that are a function of the modulation signal, and at a second output, a second control voltage that is a function of the modulation signal, c) wherein the oscillator has a first control input connected to the loop filter and has a second control input connected to the second output of the modulation unit, and is designed to generate the output signal as a function of the first control voltage and the second control voltage, d) and wherein the frequency divider is connected to the first output of the modulation unit and is designed to derive the frequency-divided signal in such a manner that it has instantaneous frequencies that are a function of the divisor values. According to the invention, the modulation unit has a capacitive voltage divider with a center tap and is designed to provide the second control voltage at the center tap. The invention further concerns a transmitting/receiving device and an integrated circuit having such a frequency modulator.

Frequency modulator

A WLAN (Wireless Local Area Network) communication device comprising a WLAN frequency synthesizer for generating a synthesizer signal suitable for modulating a transmission signal and/or demodulating a reception signal and corresponding methods and integrated circuit chips are provided. The WLAN frequency synthesizer comprises a reference oscillator for generating a first reference clock signal, a fractional-N PLL (Phase-Locked Loop) unit for receiving a second reference clock signal and converting the second reference clock signal into the synthesizer signal, and a frequency multiplier for receiving the first reference clock signal and converting the first reference clock signal into the second reference clock signal to be forwarded to the fractional-N PLL unit by multiplying the frequency of the first reference clock signal by a multiplication factor. Embodiments may provide shorter settling times and/or enhanced spurious suppression of the fractional-N PLL unit.

Frequency multiplier pre-stage for fractional-N phase-locked loops

A wireless local area network transceiver, an integrated circuit chip, a PLL (Phase Locked Loop) device and a method are provided that may reduce influences of switching noise. The frequency of an output signal of the PLL device is divided in a prescaler of the PLL device by a prescaler factor. The prescaler is operable in at least two modes with each mode having assigned a different prescaler factor. An accumulator is implemented in the PLL circuit for generating a mode switching signal for changing the mode of the prescaler. The generation of the mode switching signal is done by storing an accumulator value and processing a modulus function for updating the accumulator value. The provided technique may allow for reducing disturbances caused by switching the mode of the prescaler in the PLL circuit.

Accumulator controlled prescaler in a phased locked loop

A tunable constant GM circuit allows to compensate for temperature and process variations with high precision by correspondingly adjusting a resistance value and/or the ratio of transistor widths. Thus, in switched capacitor circuits the frequency behaviour, such as the settling time, may be controlled by providing a compensated bias to the transconductance amplifiers typically used in these circuits.

Circuit and a method for controlling the bias current in a switched capacitor circuit

A PLL frequency synthesizer able to automatically set an appropriate operating mode of the voltage controlled oscillator is provided. The voltage controlled oscillator is operable in a plurality of operating modes each defining a different operating frequency range of the voltage controlled oscillator. The appropriate operating mode is selected based on an error signal detected by a phase/frequency detector of the PLL frequency synthesizer. A window comparator is used for switching to adjacent operating modes if the error signal exceeds or falls below predefined upper and lower error voltage limits.

Growing community of inventors

Ottendorf-Okrilla, Germany

Rolf Jaehne