Intel Corporation

Nokia Corporation

Intel IP Corporation

Rolf H Kuehnis

Sankaran M Menon

Patrik Eder

Enrico David Carrieri

Jinshi Huang

Bradley H Smith

Julien Sebot

Peter Lachner

Matthew Long

Babu Trp

Robert A Dunstan

Rajaram Regupathy

Abram M Detofsky

Krishna Kumar Ganesan

Rob W Sims

Jouni Hietamäki

Miikka Merilahti

John Michael Peterson

Rehan M Sheikh

Antti Pirttimaki

Eija Maarit Hillevi Manninen

Asifur Rahman

Mohsen Fazlian

In one embodiment, a processor includes: a first plurality of intellectual property (IP) circuits to execute operations; and a second plurality of integrated voltage regulators, where the second plurality of integrated voltage regulators are oversubscribed with respect to the first plurality of IP circuits. Other embodiments are described and claimed.

System, apparatus and method for dynamic thermal distribution of a system on chip

In one embodiment, an apparatus includes interconnect circuitry to implement one or more layers of a Universal Serial Bus (USB)-based protocol. The interconnect circuitry can implement a first USB-based interface and a second USB-based interface. The apparatus further includes telemetry circuitry to generate telemetry data, cause the telemetry data to be transmitted via the first USB-based interface, detect a power state transition in the apparatus, cause the telemetry data to be buffered based on detecting the power state transition, and cause the buffered telemetry data to be transmitted via the second USB-interface based on a set interface request indicating the second USB-interface.

Dynamic functional input/output (IO) device interface selection through power state transitions

Existing multi-wire debugging protocols, such as 4-wire JTAG, 2-wire cJTAG, or ARM SWD, are run through a serial wireless link by providing the debugger and the target device with hardware interfaces that include UARTs and conversion bridges. The debugger interface serializes outgoing control signals and de-serializes returning data. The target interface de-serializes incoming control signals and serializes outgoing data. The actions of the interfaces are transparent to the inner workings of the devices, allowing re-use of existing debugging software. Compression, signal combining, and other optional enhancements increase debugging speed and flexibility while wirelessly accessing target devices that may be too small, too difficult to reach, or too seal-dependent for a wired connection.

Interfaces for wireless debugging

Techniques and mechanisms to exchange test, debug or trace (TDT) information via a general purpose input/output (I/O) interface. In an embodiment, an I/O interface of a device is coupled to an external TDT unit, wherein the I/O interface is compatible with an interconnect standard that supports communication of data other than any test information, debug information or trace information. One or more circuit components reside on the device or are otherwise coupled to the external TDT unit via the I/O interface. Information exchanged via the I/O interface is generated by, or results in, the performance of one or more TDT operations to evaluate the one or more circuit components. In another embodiment, the glue logic of the device interfaces the I/O interface with a test access point that is coupled between the one or more circuit components and the I/O interface.

Device, system and method to support communication of test, debug or trace information with an external input/output interface

In one embodiment, an apparatus includes: a first trace source to generate a plurality of first trace messages and a first local platform description identifier to identify the first trace source; a second trace source to generate a plurality of second trace messages and a second local platform description identifier to identify the second trace source; and a trace aggregator coupled to the first and the second trace sources, the trace aggregator to generate a global platform description identifier for the apparatus and output a trace stream including the global platform destination identifier, the first and second local platform description identifiers, the plurality of first trace messages and the plurality of second trace messages. Other embodiments are described and claimed.

System, apparatus and method for dynamic tracing in a system

Technologies for efficiently providing reliable compute operations for mission critical applications include a reliability management system. The reliability management system includes circuitry configured to obtain conclusion data indicative of a conclusion made by each of two or fewer compute devices of a host system. The conclusion data from each compute device pertains to the same operation. Additionally, the circuitry is configured to identify whether an error has occurred in the operation of each compute device, determine, in response to a determination that an error has occurred, a severity of the error, and cause the host system to perform a responsive action as a function of the determined severity of the error.

Technologies for efficient reliable compute operations for mission critical applications

Methods and apparatuses relating to a multiple master capable debug interface are described. In one embodiment, an apparatus includes a device circuit, a wireless connector circuit, and a switching circuit coupled between the device circuit and the wireless connector circuit to switch a debug and test mastership from the wireless connector circuit to a debug and test tool, wirelessly connected to the wireless connector circuit, to perform a debug and test operation on the device circuit.

Apparatuses and methods for a multiple master capable debug interface

System, apparatus and method for dynamic multi-source tracing in a system

In one embodiment, an apparatus includes a controller to couple between a system on chip (SoC) and an external connector of a platform. The controller may include: a digitizer to digitize platform telemetry information of the platform; and a control circuit to receive a command from a debug test system and direct the platform telemetry information to a destination in response to the command. Other embodiments are described and claimed.

System, apparatus and method for non-intrusive platform telemetry reporting using an all-in-one connector

One embodiment provides a master device in a bus system. The master device includes bus interface circuitry to exchange commands and data with a slave device in communication with the master device; and test sequence generation logic to generate at least one test sequence, each test sequence having a corresponding unique clock signal having a unique clock frequency; the test sequence generation logic also to transmit the at least one test sequence and the corresponding unique clock signal to the slave device; the test signal generation logic also to determine, based on feedback from the slave device, if the slave device is capable of communicating with the master device using the unique clock frequency.

Device throughput optimization for bus protocols

Techniques and apparatus for error and performance analysis of a computing device are described. In one embodiment, for example, an apparatus may include at least one memory and logic coupled to the at least one memory, wherein the logic is further to access at least one trace associated with at least one trace source, access timing information associated with the at least one trace, generate a plurality of waypoints for at least one trace, each of the plurality of waypoints comprising a step of at least one trace and a time stamp, and generate at least one performance benchmark log for the at least one trace, the at least one benchmark log comprising a plurality of benchmark waypoints corresponding to the plurality of waypoints.

Growing community of inventors

Portland, OR, United States of America

Rolf H Kuehnis