Infineon Technologies Austria Ag

Rolf Gerlach

Hans-Joachim Schulze

Anton Mauder

Hubert Rothleitner

Wolfgang Scholz

Philipp Seng

Daniel Pedone

Peter Tuerkes

Christian Kasztelan

A temperature protected power semiconductor device has a substrate which includes a power field effect transistor (FET) and a thermosensitive element. The power FET has a gate electrode connected to a gate, a drift region, and first and second terminals for a load current. The load current is controllable during operation by a voltage applied between the gate and the first terminal. The thermosensitive element has a first contact connected to one of the gate electrode and first terminal of the power FET, and a second contact connected to the other one of the gate electrode and first terminal. The thermosensitive element is located close to the power FET and thermally coupled thereto. The thermosensitive element is configured to cause the power FET to reduce the load current in case of an exceedance of a limit temperature of the power FET, by interconnecting the gate and first terminal.

Power semiconductor device with integrated temperature protection

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Starnberg, Germany

Rolf Gerlach