Advanced Micro Devices Corporation

Rolf Geilenkeuser

Karsten Wieczorek

Amit P Marathe

Maciej Wiatr

Kurt Taylor

Richard Heller

Eugene Zhao

John Zhang

Jörg-Oliver Weidner

Joerg-Oliver Weidner

By maintaining a substantially constant total die power during the entire lifetime of sophisticated integrated circuits, the performance degradation may be reduced. Consequently, greatly reduced guard bands for parts classification may be used compared to conventional strategies in which significant performance degradation may occur when the integrated circuits are operated on the basis of a constant supply voltage.

Compensation of operating time-related degradation of operating speed by a constant total die power mode

A method for efficiently and accurately measuring a maximum Vcalculation or failure rate and lifetime projection for microprocessors and other semiconductor products analytically scales low voltages applied to thinner oxides to thicker oxides. The expanded voltage window that is closer to the use voltage is obtained thereby to provide accurate voltage acceleration factors and max Vextraction.

Method for determining projected lifetime of semiconductor devices with analytical extension of stress voltage window by scaling of oxide thickness

A test structure for assessing the reliability of a dielectric of a circuit element in an integrated circuit includes a plurality of test circuit elements and a plurality of contact pads, wherein at least some of the test circuit elements share one or more of the contact pads. In this way, a failure event can be detected with a reduced number of contact pads, thereby significantly reducing the area of floor space occupied by the test structure.

Integrated semiconductor structure for reliability tests of dielectrics

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Dresden, Germany

Rolf Geilenkeuser