International Business Machines Corporation

Globalfoundries Inc.

Rolf Fritz

Thomas Schlipf

Ulrich Mayer

Markus Cebulla

Jan Van Lunteren

Markus Kaltenbach

Thomas Pflueger

Markus Helms

Christine Axnix

Manfred Walz

Andreas Koenig

Juergen Probst

Christopher S Smith

Cordt W Starke

Andreas Muller

Daniel Thiele

Cedric Lichtenau

Daniel D Sentler

Kirk David Lamb

Cédric Lichtenau

Thomas Buechner

Joerg Behrend

Stephan Christopher Smith

Disclosed aspects relate to a first-in-first-out (FIFO) buffer. The FIFO buffer may include an input interface to receive a set of data payloads. The FIFO buffer may include a set of buffer entry elements to store the set of data payloads. The FIFO buffer may include a set of status indicators to indicate a set of statuses of the set of buffer entry elements with respect to the set of data payloads. The FIFO buffer may include an output interface for release of the set of data payloads.

First-in-first-out buffer

Embodiments of the present invention disclose an apparatus and method for recovering a data signal in a digital transmission. A computer processor receives a data signal from a data signal input wire. The computer processor receives an external clock signal. The computer processor samples a binary bit of the data signal multiple times per clock cycle. The computer processor determines, for each sampling group, a sample and a quality measurement. The computer processor stores, for each sampling group, the sample and the quality measurement into a set of memory elements. The computer processor stores the sample from each sampling group into a first and a second delay chain. The computer processor determines a current sampling point. The computer processor transmits output corresponding to a content of the current sampling point to a data signal output wire.

Apparatus and method to recover a data signal

An improved method to compensate for coupling overhead in a distributed computing system offering a raw processing capacity, comprising an effective processing capacity () and the coupling overhead, is disclosed, wherein the distributed computing system comprises at least one computer system and at least one coupling facility. The method comprises determining a coupling efficiency, determining and adding an amount of missing processing capacity to the effective processing capacity based on the coupling efficiency in a way that the effective processing capacity of the raw processing capacity corresponds to a billable target processing capacity.

Method, data processing program, and computer program product to compensate for coupling overhead in a distributed computing system, and corresponding overhead calculator for a distributed computing system and corresponding computer system

An approach for processing data by a pipeline of a single hardware-implemented virtual multiple instance finite state machine (VMI FSM) is presented. Based on a current state and context of an FSM instance, an input token selected from multiple input tokens to enter a pipeline of the VMI FSM, and a status of an environment, a new state of the FSM instance is determined and an output token is determined. The input token includes a reference to the FSM instance. In one embodiment, the reference is an InfiniBand QP number. After a receipt by the pipeline of the first input token and prior to determining the new state of the FSM instance and determining the output token, a logic circuit selects a second input token to enter the pipeline. The second input token includes a reference to a second FSM instance.

Efficiently implementing a plurality of finite state machines

A method and program product for processing data by a pipeline of a single hardware-implemented virtual multiple instance finite state machine (VMI FSM). An input token of multiple input tokens is selected to enter a pipeline of the VMI FSM. The input token includes a reference to an FSM instance. In one embodiment, the reference is an InfiniBand QP number. After being received at the pipeline, a current state and context of the FSM instance are fetched from an array based on the reference and inserted into a field of the input token. A new state of the FSM instance is determined and an output token is generated. The new state and the output token are based on the current state, context, a first input value, and an availability of a resource. The new state of the first FSM instance is written to the array.

A method and apparatus for processing data by a pipeline of a virtual multiple instance extended finite state machine (VMI EFSM). An input token is selected to enter the pipeline. The input token includes a reference to an EFSM instance, an extended command, and an operation code. The EFSM instance requires the resource to be available to generate an output token from the input token. In response to receiving an indication that the resource is unavailable, the input token is sent to a wait room or an initiative token containing the reference and the operation code is sent to a wait queue, and the output token is not generated. Without stalling and restarting the pipeline, another input token is processed in the pipeline while the resource is unavailable and while the input token is in the wait room or the initiative token is in the wait queue.

Virtual multiple instance extended finite state machines with wait rooms and/or wait queues

Methods and corresponding test systems for generating a chip facility waveform from a series of chip snapshots. The methods including, (i) testing an integrated chip multiple times, each time increasing a clockstop delay delaying a clockstop generated by triggered error condition each time determining the state of state holding elements of the integrated circuit and (ii) testing an integrated circuit chip one time to generate a error condition and determining multiple times the states of state holding elements of the integrated circuit based on previous states of the state holding elements.

Method and system for generating an integrated circuit chip facility waveform from a series of chip snapshots

A method and logic circuit for a resource management finite state machine (RM FSM) managing resource(s) required by a protocol FSM. After receiving a resource request vector, the RM FSM determines not all of the required resource(s) are available. The protocol FSM transitions to a new state, generates an output vector, and loads the output vector into an output register. The RM FSM transitions to a state indicating that not all the resources are available and freezes an input register. In a subsequent cycle, the RM FSM freezes the output register and a current state register, and forces the output vector to be seen by the FSM environment as a null token. After determining that the required resource(s) are available, the RM FSM transitions to another state indicating that the resources are available, enables the output vector to be seen by the FSM environment, and unfreezes the protocol FSM.

Resource management finite state machine for handling resource management tasks separate from a protocol finite state machine

The invention relates to a method of optimizing a state transition function specification for a state machine engine based on a probability distribution for the state transitions. For the preferred embodiment of the invention, a B-FSM state machine engine accesses a transition rule memory using a processor cache. The invention allows improving the cache hit rate by exploiting the probability distribution. The N transition rules that comprise a hash table entry will be loaded in a burst mode from the main memory, from which the N transition rules are transferred to the processor cache. Because the comparison of the actual state and input values against each of the transition rules can immediately start after each of these rules has been received, the overall performance is improved as the transition rule that is most likely to be selected is the first to be transferred as part of the burst access.

Method and system for changing a description for a state transition function of a state machine engine

The invention relates to a method and system for the design and implementation of state machine engines. A first constraints checking step checks a state transition function created by a designer against constraints imposed by the implementation technology in order to detect all portions of the state transition function that are in conflict with the constraints. A subsequent conflict resolution step tries to determine one or more suggested ways to meet the conflicting constraints, by investigating how the original state transition function can be modified such that all constraints are met. A final presentation and selection step provides the designer textual and/or graphically results of the constraints check and suggested modifications. The modifications can be accepted interactively, or the state transition function can be changed manually. In the latter case, the modified state transition function will be processed starting again with the constraints checking step.

A system and method of implementing multiple programmable finite state machines using a shared transition table is disclosed, the method including forming a plurality of finite state machine cores such that an amount of the plurality of finite state machine cores is unchangeable, forming a state transition array, and forming a routing network such that the forming the plurality of associated state transition elements is realized.

Multiple parallel programmable finite state machines using a shared transition table

A method and device for parameter independent buffer underrun prevention in a data communication system includes a buffer for compensating for a difference in the rate of flow of data having a write port and a read port. After a commencement of writing data into the buffer, a predetermined delay time occurs. When the delay time has passed, reading data out from the buffer starts. Then the length of a time gap between the completion of writing data into the buffer and completion of reading data out from the buffer is determined. Finally, the length of the predetermined delay time is decreased by a first value if the length of the time gap is larger than a specified tolerance value and the length of the predetermined delay time is increased by a second value if the length of the time gap is smaller than the specified tolerance value. The provided method and device advantageously adjusts to systems having dynamically varying parameters, e.g., processors or other devices having a variable clock rate due to power-saving-modes.

Method and device for parameter independent buffer underrun prevention

A non-obtrusive activity monitor is proposed for advantageously monitoring and tracing disjunct, concurrent computer system operations in heavily queued computer systems. For each traced and pending computer system operation, the monitor uses a hardware implementation of an event triggered operation graph to trace the path of the computer system operation through the computer system. For each followed path, a unique signature is generated that significantly reduces the amount of trace data to be stored. In a preferred embodiment, the trace information is stored together with a time stamp for debugging and measuring queuing effects and timing behavior in a computer system.

Growing community of inventors

Waldenbuch, Germany

Rolf Fritz