Freescale Semiconductor,inc.

Nxp USA, Inc.

Rolf Dieter Schlagenhaft

Michael Rohleder

Dirk Wendel

Robert Cristian Krutsch

Oliver Bibel

Alistair Robertson

Markus Baumeister

Stefan Doll

Timothy J Strauss

Joachim Kruecken

The present application relates to an apparatus for verifying fragment processing related data and a method of operating thereof. The fragment shader unit is coupled to the at least one data buffer. A fragment shader unit of a graphics processing pipeline receives fragment data and records fragment processing related data in the at least one data buffer on processing one or more fragments in accordance with the received fragment data. A comparator unit coupled to the at least one data buffer compares the recorded fragment processing related data in the at least one data buffer to reference data and issues a fault indication signal in case the recorded fragment processing related data and the reference data mismatch.

Apparatus and method for verifying fragment processing related data in graphics pipeline processing

The present application relates to an apparatus for verifying the integrity of image data comprising mapped texture data is provided and a method of operating thereof. A fragment shader unit is coupled to first and second frame buffers and at least one texture buffer. A first texture sampler unit is configured to output texture mapped fragments to the first frame buffer. A second texture sampler unit is configured to output texture mapped fragments to the second frame buffer. A comparator unit is further configured to compare the image data stored in the first frame buffer and in the second frame buffer. A fault indication signal is issued in case the image data of the first and the second frame buffers mismatch.

Apparatus and method for verifying image data comprising mapped texture image data

High frequency detection of interrupts includes incrementing a count by a first number in response to at least one interrupt. The count is decremented by a second number in response to a clock if the count is greater than zero. An interrupt rate is determined from the count. A fault collection unit (FCU) is updated when the interrupt rate exceeds a threshold.

Detector for high frequency interrupts

An integrated circuit comprises a write bus coupled to a register for storing control data. A storage unit is arranged to store reference signature data encoding a reference collective state of the register. First logic circuitry generates actual signature data encoding the actual collective state of the register. Second logic circuitry is coupled to the storage unit, receives the actual signature data and compares the actual signature data with the reference signature data. The second logic circuitry comprises an alert output to provide an alert signal in response to the comparison identifying a difference between the actual signature data and the reference signature data, thereby ensuring detection of a data integrity error in respect of the register. An alert inhibitor comprises a control input and is responsive to the control input and arranged to inhibit selectively onward propagation of the alert signal from the alert output.

Integrated circuit and method of detecting a data integrity error

An error correcting device is provided that has an input connectable to receive one or more data units, an error detection module arranged to identify a presence of one or more errors in a received data unit of the one or more data units and to provide an error detection signal for the received data unit, an error correction module arranged to perform an error correction processing on the received data unit and provide a corrected data unit, and a correction evaluation module arranged to perform a comparison of the received data unit with the corrected data unit and to generate a correction error signal depending on a result of the comparison and the error detection signal.

Error correcting device, method for monitoring an error correcting device and data processing system

A circuit comprises a clock tree for distributing a clock signal. A first counter is arranged at a first point in the clock tree. Upon detecting a triggering edge in the clock signal, the first counter sets a first current count equal to a first delayed count. After a first delay, the first counter sets the first delayed count equal to the first current count plus an increment. A second counter is arranged at a second point in the clock tree. Upon detecting a triggering edge in the clock signal, the second counter sets a second current count equal to a second delayed count. After a second delay, the second counter sets the second delayed count equal to the second current count plus the increment. A comparator compares the first current count and the second current count. The first point and the second point are not the same, or the second delay is longer than the first delay.

Clock glitch detection

A logic built-in self test (LBIST) system comprises a device under test having a first plurality of first bistable multivibrator circuits an LBIST controller, and a second plurality of second bistable multivibrator circuits. Each second bistable multivibrator circuit is coupled to a corresponding first bistable multivibrator circuit to swap a second state value kept by the second bistable multivibrator circuit with a first state value kept by the corresponding first bistable multivibrator circuit depending on a first control signal from the LBIST controller and the second bistable multivibrator circuits are coupled to form one or more scan chains when receiving a second control signal from the LBIST controller.

Growing community of inventors

Poing, Germany

Rolf Dieter Schlagenhaft