International Business Machines Corporation

Rolf B Hilgendorf

Cedric Lichtenau

Michael Fan Wang

Thomas Schlipf

Hartmut R Schwermer

Harry S Barowski

Christopher Michael Abernathy

Peter Anthony Sandon

Thomas Pflueger

Hans-Werner Tast

Jonathan James DeMent

Gerard M Salem

Juergen Haess

Gilles Gervais

Ulrich Weiss

Cédric Lichtenau

Jens Kuenzer

Wolfram M Sauer

Hartmut Ulland

Mathew I Ringler

Dana J Thygesen

Oliver Laub

Siegfried Neuber

Jurgen Hass

Werner Soell

Power is conserved by dynamically applying clocks to execution units in a pipeline of a microprocessor. A clock to an execution unit is applied only when an instruction to the execution unit is valid. At other times when the execution unit needs not to be operational, the clock is not applied to the execution unit. In a preferred embodiment of the invention, a dynamiclock-control unit is used to provide a control signal to a local clock buffer providing a local clock to an execution unit.

Dynamic power management in an execution unit using pipeline wave flow control

An apparatus, a method, and a computer program are provided for the generation of constant incremental increases while changing core clock frequencies. In computer systems, oftentimes frequency changes are useful. Maintaining the clocking ability of the computer system, though, can be a difficult task. To maintain the time keeping ability, time base logic is utilized with the free-running clock, which can be frequency limited. However, a plurality of communication channels in conjunction with an adder system is employed to effectively adjust for an ever increasing frequency to allow for a effective timekeeping regardless of the core frequency.

Timer facility for high frequency processors with minimum dependency of processor frequency modes

A synchronization system capable of simultaneously resetting frequency divide-by counters () of multiple processors (A, B) to zero regardless of the divide-by frequency signal (Mclk/n signal ()) and regardless of the magnitude of the clock mesh delays experienced by the Mclk/n signals in the processors. The synchronization system includes a mesh delay circuit () for each processor that simulates in the undivided signal (Mclk/1 signal ()) the clock mesh delay experienced by the Mclk/n signal in that processor so as to provide an Lclk signal (). A phase detector detects the phase offset between the Mclk/n signal and the Sysclk signal () and sends an asynchronous offset signal () to a counter re-setter () that resets the divide-by counter to zero based on the offset signal.

System and method for synchronizing divide-by counters

This invention is a method and system for hybrid prediction of load addresses and/or values. The new scheme for value prediction provides prediction based on last values and strides, as well as context prediction, without the use of a sophisticated switching scheme between several predictors. The system collects patterns of deltas of subsequent values instead of the values itself in a first table. Thus, a last value prediction can be achieved by predicting a 'pattern' of just one stride equal to zero. A stride predictor uses a pattern of one constant stride. And a certain pattern of values is modeled by recording the pattern of deltas between the values and adding the deltas to the last value. The switching scheme is inherently included in the system itself and operates basically by immediate evaluation of counters in the pattern history table.

Universal load address/value prediction using stride-based pattern history and last-value prediction in a two-level table scheme

The present invention provides for supporting an on chip-timer facility and, more particularly, to the generation of a constant time incremental increase while changing core mesh-clock frequency. A latch is coupled to the output of a first free-running clock. An inverter is coupled to the output of the first latch. At least one other secondary latch is coupled to the output of the first latch. An edge detector is coupled to the output of the secondary latch. An incrementer or decrementer is coupled to the output of the edge detector. A memory is coupled to the output of the incrementer or decrementer.

Time-base implementation for correcting accumulative error with chip frequency scaling

An apparatus and a method for performing subroutine call and return operations in a computer having a processor with an instruction prefetch mechanism which includes a branch history table for storing target addresses of a plurality of branch instructions found in an instruction stream. The branch history table 22 contains a potential call instruction tag 37 and a return instruction tag 39. For each potential subroutine call instruction found in a prefetch instruction stream an address pair containing the call target address and the next sequential instruction address of the instruction is stored in a return identification stack 24. Subsequently detected branch instructions initiate an associative search on the next sequential instruction part in the return identification stack where a matching entry identifies the branch instruction as a return instruction. The address pair contained in the matching entry is then transferred to a return cache 30 which is arranged in parallel to the branch history table. The branch history table and the return cache are simultaneously accessed in the same operation cycle with the address 28 of each prefetched instruction, and if by the access a return instruction tag is found, the next sequential instruction address from the return cache is used as return address. A return cache update 32 is performed in response to a branch instruction in the instruction stream by a lookup of the return cache for an entry having a corresponding target address and by replacing the next sequential instruction address in said entry by the next sequential address of said branch instruction.

Apparatus and method for performing subroutine call and return operations

A method for addressing internal instructions in an out-of-order processor is proposed, which allows for an efficient register renaming even in case internal instructions are issued to a multitude of window buffers. In this case, it is not clear how internal instructions that stem from one external instruction can be indicated as being 'related'. In the method proposed, a common instruction identifier is assigned to each of the internal instructions of a group of internal instructions representing an external instruction. Furtheron, an offset identifier is assigned to each of said internal instructions in order to be able to unambiguously identify each of said internal instructions. These two identifiers are used as a tag, in order to be able to resolve data dependencies. By use of the invention, exception handling, recovery of mispredicted branches, and committing related instructions corresponding to one external instruction is simplified.

Identification of related instructions resulting from external to

The invention provides an apparatus and a method for converting instructions of a code A to instructions of a code B. Said conversion is performed by obtaining rearrangement information, which corresponds to the instruction that is to be converted, from a table. Said rearrangement information is then used to rearrange the instruction elements of the initial instruction, in order to generate instructions of code B, which functionally corresponds to said initial instruction. Said rearrangement can be performed by multiplexing means, which use said instruction elements of the initial code A instruction as input, and which select one of said instruction elements, or the content of another register, and forward this selected data to the instruction that is to be generated. Said rearrangement information is directly used to control the selection performed by said multiplexers.

Dynamic conversion between different instruction codes by recombination

A method and system for the design verification of logic units capable of providing verification of a logic unit design prior to chip production. At least one test unit is coupled to a logic unit via an interface. The test unit includes a set of operations which are applied to the logic unit. The selection of test operations to be applied to the logic unit and the determination of the start times thereof are executed randomly and independently of each other. Thus, with the present method and system two parameters of the test operation generating event: the sequence of the test operations, and the temporal relationship between the test operations, are independently and randomly modified.

Method and system for the design verification of logic units and use in

A system buffers first and second data buses having asynchronous, different frequency clocks. The system comprises a data buffer interposed between the first and second data buses to receive data from the first bus and supply data to the second bus. The also comprises a write address generator, coupled to the first bus to receive a data available signal and coupled to the data buffer, for generating an address in the data buffer to store the data received from the first bus. The data available signal increments the write address generator. A load record register is coupled to receive an indication that data is being written from the first data bus into the data buffer, and tracks locations in the data buffer which have received data from the first data bus. A read address generator is coupled to the data buffer, and generates an address of the next data, if any, that is stored in the data buffer to be read onto the second data bus. A conversion and comparison circuit is coupled between the read address generator and the load record, and determines if the address in the data buffer generated by the read address generator contains data to be read onto the second data bus, and if so, enables transmission of the data at the address to the second data bus and enables incrementing of the read address generator when or after said data is read to the second data bus.

System for transferring data between asynchronous data buses with a data

A method and an apparatus to avoid a deadlock in a computer system with several busses connected by a bus adapter. If units of different busses of the computer system simultaneously start operations for which more than one bus is needed, it may come to a deadlock. By introducing a BUS SUSPEND signal to one of the busses and adapting the bus-protocol to honor this signal at distinct time slots, deadlock situations are avoided.

Method and apparatus for avoiding deadlock in a computer system with two

A bus arbitration scheme for controlling access or mastership of a bus is disclosed. Priority of access to the bus is based not only on the time relationship of the requests for use of the bus arriving at the arbiter but also on the relative priority of each request. Thus a higher priority request will gain access to the bus before a lower priority one even if this latter request arrived at the arbiter first. The arbitration scheme is implemented by a series of logic gates.

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Boeblingen, Germany

Rolf B Hilgendorf