Siemens Aktiengesellschaft

Infineon Technologies Ag

Soitec

Qimonda Ag

Infineon Technologies LLC

Roland Thewes

Werner Weber

Christian Paulus

Doris Schmitt-Landsiedel

Ralf Peter Brederlow

Paul-Werner Von Basse

Michael Bollu

Alexander Frey

Meinrad Schienle

Richard Ferrant

Erdmute Wohlrab

Christian Pacha

Stefan Prange

Helmut Schneider

Wolfgang Hoenlein

Stefan Jung

Franz Hofmann

Walter Gumbrecht

Siegfried Schwarzl

Martin Kerber

Joerg Vollrath

Gerhard Enders

Konrad Mund

Richard Johannes Luyken

Till Schl&ouml;sser

Reinhard Gabl

Wolfram Wersing

Till Schlösser

Bjorn-Oliver Eversmann

Andreas Luck

Ute Kollmer

Martin Jenkner

Carsten Linnenbank

Ulrich Schaper

Jeongwook Koh

Hugo Van Den Berg

Andreas Luck, Deceased

Stefan Kuehn

Michael Kleiner

Michael Beck

Matthias Schreiter

Peter Lahnor

Guido Stromberg

Peter Fromherz

Jens Sauerbrey

Gunther Plasa

Ivo Koren

Martin Wittig

Birgit Holzapfl

Markus Seitz

Doktorand Andreas Luck

Doris Schmitt-Lansiedel

Thomas Kopley

Stephan Sauter

By Manfred Luck, Legal Representative

By Inge Booken, Legal Representative

By Inge Booken, Heir

By Manfred Luck, Heir

Hofmann Franz

Michael Otto

Tamara Birkenmaier

Claudio Stagni Degli Esposti

Björn-Oliver Eversmann

Sylvain Briole

This invention concerns a semiconductor memory device comprising: at least one sense amplifier circuit for reading data sensed from selected memory cells in a memory array,&#x2014;at least one reference circuit, each reference circuit being a replica of the sense amplifier circuit and having an output through which the reference circuit delivers an output physical quantity, a regulation network providing a regulation signal to each sense amplifier circuit and each reference circuit, wherein the regulation signal is derived from an averaging of the output physical quantity over time and/or space, wherein the regulation network comprises a control unit configured to sum up the physical quantities of each output of the reference circuit and a target mean value, the control unit delivering a regulation signal based on the sum, the regulation signal being fed in to each regular sense amplifier circuit and to each reference circuit.

Memory device with dynamically operated reference circuits

The disclosure relates to semiconductor memory devices and related methods. A semiconductor memory device comprises: a single-ended sense amplifier circuit for reading data sensed from selected memory cells in a memory array, the sense amplifier having a first node used to feed in a reference signal, a second node coupled to a bit line, and sense transistors responsible for amplifying the content of a selected memory cell during a sense operation, a reference circuit having replica transistors of the sense transistors and further comprising a regulation network designed so that each replica transistor operates in a stable operating point, and wherein the regulation network generates a control voltage that is applied to the sense amplifier circuit.

Reference circuit to compensate for PVT variations in single-ended sense amplifiers

A circuit for sensing a difference in voltage on a pair of dual signal lines comprising a first signal line and a second signal line complementary to the first signal line, comprising:

Circuit and method for sensing a difference in voltage on a pair of dual signal lines, in particular through equalize transistor

The invention relates to a sense amplifier for sensing and amplifying data stored in a memory cell, the sense amplifier being connected between a bit line (BL) and a reference bit line complementary (/BL) to the first bit line and comprising: a sense circuit (SC) capable of providing an output indicative of the data stored in the memory cell; and a precharge and decode circuit (PDC) comprising a pair of dual gate transistors (T, T) for precharging the first and second bit lines during a precharge operation and for transferring the output provided by the sense circuit to a data line (LIO,/LIO) during a read operation.

Sense amplifier with dual gate precharge and decode transistors

A differential sense amplifier for sensing data stored in a plurality of memory cells of a memory cell array, including a first CMOS inverter having an output connected to a first bit line (BL) and an input connected to a second bit line complementary to the first bit line and a second CMOS inverter having an output connected to the second bit line (/BL) and an input connected to the first bit line. Each CMOS inverter includes pull-up and pull-down transistors, wherein the sources of either of the pull-up transistors or the pull-down transistors are electrically coupled and connected to a pull-up voltage source or a pull-down voltage source without an intermediate transistor between the sources of the transistors and the voltage source.

Differential sense amplifier without switch transistors

The invention relates to a differential sense amplifier for sensing data stored in a plurality of memory cells of a memory cell array, including a first CMOS inverter having an output connected to a first bit line and an input connected to a second bit line complementary to the first bit line, and a second CMOS inverter having an output connected to the second bit line and an input connected to the first bit line (BL). Each CMOS inverter includes a pull-up transistor and a pull-down transistor, with the sense amplifier having a pair of precharge transistors arranged to be respectively coupled to the first and second bit lines, to precharge the first and second bit lines to a precharge voltage. The precharge transistors are constituted by the pull-up transistors or by the pull-down transistors.

Differential sense amplifier without dedicated precharge transistors

A differential sense amplifier for sensing data stored in a plurality of memory cells of a memory cell array, including a first CMOS inverter having an output connected to a first bit line and an input connected to a second bit line complementary to the first bit line, and a second CMOS inverter having an output connected to the second bit line and an input connected to the first bit line. Each CMOS inverter includes a pull-up transistor and a pull-down transistor, and the sense amplifier has a pair of pass-gate transistors arranged to connect the first and second bit lines to a first and a second global bit lines. Advantageously, the pass-gate transistors are constituted by the pull-up transistors or the pull-down transistors.

Differential sense amplifier without dedicated pass-gate transistors

A biosensor array having a substrate, a plurality of biosensor zones arranged on the substrate, each of which has a first terminal and a second terminal, at least one drive line and at least one detection line, the at least one drive line being electrically insulated from the at least one detection line. In each case the first terminal of each biosensor zone is coupled to precisely one of the at least one drive line and the second terminal of each biosensor zone is coupled to precisely one of the at least one detection line, and at least one of the at least one drive line and at least one of the at least one detection line is coupled to at least two of the biosensor zones. The biosensor array also has a drive unit for providing an electrical drive signal, a detection unit for detecting an electrical detection signal resulting from the electrical drive signal, and a selection unit that couples the drive unit to the drive line of a biosensor zone to be selected and the detection unit to the detection line of the biosensor zone to be selected, whereby the biosensor zone is selected.

Biosensors array and method for operating a biosensor array

A sensor arrangement including a control circuit is disclosed. In at least one embodiment, at least one sensor electrode can be charged and/or discharged therewith and a comparator unit for the comparison of a provided voltage for the at least one electrode with a reference voltage. A duration necessary for the charging/discharging of the at least one sensor electrode is determined, whereby, from the determined duration, it is determined whether a sensor event, in the form of a hybridization between trap molecules and the particles for recording, has occurred.

Sensor arrangement and method for detecting a sensor event

The invention relates to an arrangement comprising a logarithmizing unit and a subtracting unit, wherein the subtracting unit has an output at which a voltage value linearly proportional to the temperature can be tapped off.

Arrangement, use of an arrangement, reference voltage source and method for generating a voltage value linearly proportional to the temperature

The invention relates to a measuring arrangement, a semiconductor arrangement and a method for operating a reference source, wherein at least one semiconductor component and a voltage source are connected to a measuring unit and the measuring unit provides a measured value that is proportional to the number of defects.

Measuring arrangement, semiconductor arrangement and method for operating a semiconductor component as a reference source

A semiconductor memory has a plurality of read amplifiers to which a pair each of two complementary bit lines is connected, wherein the semiconductor memory includes at least one switching element each for each bit line, by which at least a partial section of the bit line may be electrically decoupled from the read amplifier, and wherein the semiconductor memory controls the first switching element so that the first switching element, when reading out and/or refreshing any memory cell connected to the bit line, temporarily electrically decouples at least the partial section of the bit line from the read amplifier.

Semiconductor memory and method for operating a semiconductor memory

A semiconductor memory having read amplifier strips having a plurality of read amplifiers and having memory cell fields which have a plurality of memory cells connected to bit lines is disclosed. The read amplifier strips include at least two outer read amplifier strips between which the remaining read amplifier strips and the memory cell fields are arranged, wherein adjacent to at least one of the outer read amplifier strips, a reference circuit field is arranged, which has reference lines and reference circuit elements connected thereto, and wherein the reference lines are shorter than the bit lines of the memory cell fields.

A circuit arrangement, an electrochemical sensor, a sensor arrangement, and a method for processing a current signal provided by a sensor electrode are disclosed. The circuit arrangement includes a sensor electrode, a first circuit unit, electrically coupled to the sensor electrode and a second circuit unit, including a first capacitor, whereby the first circuit arrangement is embodied to hold the electrical potential of the sensor electrode in a given first reference range about a set electrical potential and, when the sensor electrode potential falls outside the first reference range, the first capacitor and the sensor electrode are coupled such that a matching of the electrical potentials is possible. The second circuit unit is embodied such that, when the electrical potential of the first capacitor falls outside a second reference range, this event is detected and the first capacitor brought to a first electrical reference potential.

Potentiostatic circuit arrangement on a biosensor for digitisation of the measured current

In one embodiment, an integrated circuit includes a memory array having a plurality of capacitors for storing data of an initial state in the memory array in an initial state. The integrated circuit also includes circuitry for occasionally inverting the data stored by the plurality of capacitors and tracking whether the current state of the data stored by the plurality of capacitors corresponds to the initial state. The circuitry inverts the data read out of the memory array during a read operation when the current state of the data does not correspond to the initial state.

Method and apparatus for reducing charge trapping in high-k dielectric material

Growing community of inventors

Gröbenzell, Germany

Roland Thewes