Integrated Device Technology, Inc.

Roland T Knaack

Yue Yu

Craig DeSimone

Alejandro F Gonzalez

David Stuart Gibson

Scott Herrington

Garret Davey

Robert J Proebsting

Mario F Au

Tak Kwong Wong

Al Xuefeng Fang

Bruce Lorenz Chin

Jon R Williamson

Paul Joseph Murtagh

Alan Wolfram Glaser

Mario Montana

Declan McDonagh

Declan P McDonagh

Bamdhamravuri S Satishbabu

Stewart Speed

Srinivas Satish Babu Bamdhamravuri

Uksong Kang

Bradley C Luis

Srinivas S B Bamdhamravuri

Shawn Giguere

An apparatus includes a control circuit comprising (i) a first differential data strobe input/output circuit having a first set of driver and termination control inputs and (ii) a second differential data strobe input/output circuit having a second set of driver and termination control inputs. The first and the second sets of driver and termination control inputs are independently programmable. The first and the second differential data strobe input/output circuits operate in a first mode when the first differential data strobe input/output circuit is connected to a first memory device having a first data width and the second differential data strobe input/output circuit is connected to a second memory device having the first data width. The first and the second differential data strobe input/output circuits operate in a second mode when the first differential data strobe input/output circuit and the second differential data strobe input/output circuit are connected in parallel to a single memory device having a second data width.

Support for multiple widths of DRAM in double data rate controllers or data buffers

An apparatus includes a plurality of memory devices and a control circuit. The control circuit may be configured to operate with the memory devices having a first data width in a first mode and with the memory devices having a second data width in a second mode. The control circuit may be configured to implement two differential data strobe input/output circuits. The differential data strobe input/output circuits each may have driver and termination control inputs that are independently programmable. The differential data strobe input/output circuits may be configured to be connected in parallel when the control circuit is operating in the second mode.

Double data rate controllers and data buffers with support for multiple data widths of DRAM

Overvoltage protection circuits include a combination of an overvoltage detection circuit and a voltage clamping circuit that inhibits sustained overvoltage conditions. An overvoltage detection circuit can include first and second terminals electrically coupled to first and second power supply signal lines, respectively. This overvoltage detection circuit may be configured to generate a clamp activation signal (CAS) in response to detecting an excessive overvoltage between the first and second power supply signal lines. This CAS is provided to an input of the voltage clamping circuit, which is electrically coupled to the first power supply signal line and configured to sink current from the first power supply signal line in response to the CAS. The voltage clamping circuit may be configured to turn on and sink current from the first power supply signal line in-sync with a transition of the CAS from a first logic state to a second logic state.

Overvoltage protection circuits and methods of operating same

A packaged integrated circuit device includes a nonvolatile memory device and a programmable clock driver circuit therein. The memory device may be provided as an EEPROM device that is disposed on a first integrated circuit substrate and the programmable clock driver circuit may be disposed on a second integrated circuit substrate. The programmable clock driver circuit includes a control circuit and a clock generator therein. The control circuit is configured to detect an error(s) in configuration data that is used by the programmable clock driver circuit. This configuration data is read from the nonvolatile memory and stored in volatile program registers during program restore operations. The control circuit is further configured to automatically idle the clock generator in response to detecting the error in the configuration data. This automatic idling of the clock generator may include operations to set the clock generator at a default setting (e.g., minimum frequency), which applies to all output banks of the driver circuit.

Programmable clock drivers that support CRC error checking of configuration data during program restore operations

Clock signal generators include an integrated circuit chip having a PLL-based or DLL-based clock driver therein. The clock driver is configured to support generation of a plurality of clock signals having different frequencies in a range between 1 and 1/N times a frequency of an internal clock signal and full-period programmable skew characteristic, where N is a positive integer greater than one. The clock driver also includes a divide-by-N clock generator that is configured to generate N divide-by-N clock signals that have the same frequency but are phase shifted relative to each other. This clock generator operates in response to a first skew signal having a frequency equal to the frequency of the internal clock signal. A one-of-N select circuit is provided. This select circuit is configured to select one of the N divide-by-N clock signals in response to a time unit position signal. A synchronization unit is electrically coupled to an output of the divide-by-N clock generator circuit and is synchronized to the first skew signal. The synchronization unit is also coupled to an output buffer that is configured to drive an off-chip load with the selected divide-by-N clock signal having the desired skew characteristic.

Clock signal generators having programmable full-period clock skew control

An integrated circuit chip includes a plurality of independent FIFO memory devices that are each configured to support all four combinations of DDR and SDR write modes and DDR and SDR read modes and collectively configured to support all four multiplexer, demultiplexer, broadcast and multi-Q operating modes. The multi-Q mode of operation supports write path queue switching that is free of write word fall-through and read path queue switching that is free of read word fall-through. The multi-Q mode also supports write path queue switching on every write cycle in both SDR and DDR write modes and independent read path queue switching on every read cycle in both SDR and DDR read modes.

Multi-FIFO integrated circuit devices that support multi-queue operating modes with enhanced write path and read path queue switching

An integrated circuit chip includes a plurality of independent FIFO memory devices that are each configured to support all four combinations of DDR and SDR write modes and DDR and SDR read modes and collectively configured to support all four multiplexer, demultiplexer, broadcast and multi-Q operating modes.

Integrated DDR/SDR flow control managers that support multiple queues and MUX, DEMUX and broadcast operating modes

Fully-buffered dual in-line memory modules (FB-DIMM) include advanced memory buffers (AMBs) having enhanced skew, slew rate and output impedance control. The AMB includes user accessible registers that can be programmed to carefully control the edge placement (or phase) of signals generated from the AMB to multiple DRAMs on the module. This control of edge placement, which may be performed independently for each group of signals: clock (CLK, CLK#), command (RAS, CAS, WE), address (including bank address), data (DQ) and data strobe (DQS), provides 360 degrees of control (or one period). This means that any group of signals can be moved independently by one complete period relatively to any other group.

DRAM interface circuits having enhanced skew, slew rate and impedance control

Clock signal generators having programmable full-period clock skew control and methods of generating clock signals having programmable skews

Methods of testing integrated circuits to include data traversal path identification information include the steps of transferring test data into an integrated circuit containing devices therein and then controlling operation of the integrated circuit so that the test data traverses a first path through the devices. At least a portion of the test data and an identification of at least a first portion of the first path are then retrieved from the integrated circuit. This retrieving step may be preceded by the step of overwriting a first portion of the test data with an identification of a first portion of the first path. In the case of a buffer memory device, an identification (e.g., address) of a current write register (receiving test data) may be &ldquo;tagged&rdquo; to a series of test words written into the current write register during test mode operation. Similarly, when the test data is ultimately read from the buffer memory device, an identification of a current read register may be &ldquo;tagged&rdquo; to the series of test words being read from the current read register. The tagged identification may be interleaved into the stream of test data being read from the current read register, may be overwritten into the stream or the address may be separately stored in the device and then provided (along with other path identification and status information) as a serial or parallel stream of identification data from a dedicated test I/O pad.

Methods of testing integrated circuits to include data traversal path identification information and related status information in test data streams

Multi-port memory arrays having partitioned registers therein are provided. The registers are partitioned into subarrays so that at least two columns of a selected register can be simultaneously written to (or read from) using first and second input/output driver circuits. These first and second input/output driver circuits are electrically coupled to respective read and write data ports at opposing ends of the memory array. Control logic and first and second input/output driver circuits are provided for writing a first portion of a word of data into a first subarray while simultaneously writing a second portion of the word of data into a second subarray. Here, the first and second portions may comprise the least significant and most significant bytes of the word of data. The first input/output driver circuit is also electrically coupled to first read and write data lines at a first end of the memory array and the second input/output driver circuit is electrically coupled to second read and write data lines at a second end of the memory array. A data flow control circuit containing a crosspoint switch is also provided for routing input and output data between input and output registers and the first and second input/output driver circuits. The data flow control circuit, preferred arrangement of memory cells and dual input/output driver circuits also enables 2.times., 1.times. and 1/2.times. word width capability which can be selected by a user, for example.

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Duluth, GA, United States of America

Roland T Knaack