Advanced Micro Devices Corporation

Globalfoundries Inc.

Roland Stejskal

Klaus Hempel

Jan Hoentschel

Andy C Wei

Sven Beyer

Thilo Scheiper

Markus Lenski

Uwe Griebenow

Andreas Kurz

Ralf Van Bentum

Stephan Kruegel

In a replacement gate approach, the semiconductor material or at least a significant portion thereof in a non-transistor structure, such as a precision resistor, an electronic fuse and the like, may be preserved upon replacing the semiconductor material in the gate electrode structures. To this end, an appropriate dielectric material may be provided at least prior to the removal of the semiconductor material in the gate electrode structures, without requiring significant modifications of established replacement gate approaches.

Semiconductor device comprising metal gates and semiconductor resistors formed on the basis of a replacement gate approach

By locally heating isolation trenches with different annealing conditions, a different magnitude of intrinsic stress may be obtained in different isolation trenches. In some illustrative embodiments, the different anneal temperature may be achieved on the basis of an appropriate mask layer, which may provide a patterned optical response for a lamp-based or laser-based anneal process. Consequently, the intrinsic stress of isolation trenches may be specifically adapted to the requirements of circuit elements, such as N-channel transistors and P-channel transistors.

Trench isolation structure having different stress

By performing an anisotropic resist modification prior to the actual resist trimming process, the profile of the end portions of the resist features may be significantly enhanced, for instance by providing substantially vertical sidewall portions. Consequently, an overlap of gate electrodes with the respective isolation structures may be obtained, while nevertheless the probability for a short circuit between opposing end portions of the gate electrodes may be significantly reduced, thereby providing the potential for further scaling down device dimensions.

Method of patterning gate electrodes by reducing sidewall angles of a mask layer

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Freital, Germany

Roland Stejskal