Texas Instruments Corporation

Roland Sperlich

Huanzhang Huang

Lei Ding

Fernando Alberto Mujica

Vijayalakshmi Devarajan

Gregory Copeland

Wesley Ray

Dushmantha Bandara Rajapaksha

Anant Shankar Kamath

Yanli Fan

Charles M Branch

Mark Edward Wentroble

Zigang Yang

Lokesh Kumar Gupta

Milind Anil Borkar

Weicheng Zhang

Richard Edwin Hubbard

Maxwell G Robertson

Abhijeeth Aarey Premanath

Dejan Radic

Amer H Atrash

William Louis Abbott

Hardik Prakash Gandhi

Lars Jorgensen

Carson Arthur Wick

A semiconductor package includes a transformer having a primary winding and a secondary winding. The primary winding has first and second terminals and a pair of taps. The secondary winding has first and second terminals and a pair of taps. The semiconductor package includes first and second data transfer circuits, a bridge, and a rectifier. The first data transfer circuit is coupled to the pair of taps of the primary winding. The second data transfer circuit is coupled to the pair of taps of the secondary winding. The bridge is coupled to the first and second terminals of the primary winding. The rectifier is coupled to the first and second terminals of the secondary winding.

Data and power isolation barrier

A lead frame for a multi-chip module includes a first conductor structure disposed on a substrate and having first and second arms linked at an angle. The first conductor structure is connected to ground. The lead frame also includes a second conductor structure disposed on the substrate and connected to a voltage supply. The second conductor structure is spaced apart and electrically isolated from the first conductor structure. The first and the second conductor structures are arranged to flank a plurality of integrated circuits (ICs) including one or more surge protection ICs disposed on the substrate. The first conductor structure is electrically connected to the plurality of ICs to provide electrical connections to ground, and the second conductor structure is electrically connected to the plurality of ICs to provide electrical connections to the voltage supply.

Lead frame for multi-chip modules with integrated surge protection

Two CAN bus transceivers utilized in a single integrated circuit package with the CAN bus connections between the two transceivers being inverted. Thus, one transceiver is connected to the CAN bus high and low lines while the other transceiver is connected to the CAN bus low and high lines. Both transceivers power up in a standby condition and each transceiver is monitoring for wake up signals on the CAN bus. The transceiver that is correctly connected to the CAN bus detects wake up signals. When the wake up signals are detected at that transceiver, that transceiver is brought to full operating state and the other transceiver is placed in a full standby condition. Additional input resistance is provided with each transceiver to maintain the proper input resistance for the integrated circuit.

Control area network (CAN) transceivers with automatic polarity detection

A driver includes first and second resistors coupled to a supply voltage and coupled to pairs of main transistors at positive and negative output nodes. The first and second pairs of main transistors provide emphasis and de-emphasis on the positive and negative output nodes. The driver also includes a delay inverter, a pull up booster and a pull down booster. The delay inverter delays and inverts each of a pair of differential input signals to provide delayed and inverted differential signals. The pull up booster provides a bypass current path that bypasses the first and second resistors but includes at least some of the first and second pairs of main transistors. The pull down booster provides an additional current path from the supply voltage through the first or second resistor to ground.

Differential driver with pull up and pull down boosters

A serial communication circuit (FIG.) is disclosed. The circuit includes an equalizer circuit () arranged to receive a data signal (CH) and produce an equalized data signal. A log detector circuit () receives the data signal and produces a power signal indicating a power level of the data signal. A decision circuit () receives the power signal and produces a select signal. A first selection circuit () receives a plurality of first correction signals and applies one of the first correction signals to the equalizer circuit in response to the select signal.

Closed-loop high-speed channel equalizer adaptation

Conventional transceivers do provide some compensation for in-phase/quadrature (I/Q) imbalance. However, these techniques do not separately compensate for I/Q imbalance for the transmitter and receiver sides of the transceiver. Here, a transceiver is provided that allows for compensation of I/Q imbalance in the transmitter and receiver irrespective of the other to allow for a more accurate transceiver.

Joint transmit and receive I/Q imbalance compensation

Systems and methods for identifying a transmission channel response and a feedback channel response from a plurality of composite system responses are disclosed. A plurality of shifted feedback signals are created by shifting a feedback signal frequency by a plurality of first offset values and/or by shifting a transmission signal frequency by a plurality of second offset values. The feedback signals are compared to an input signal to identify the transmission channel response and/or a feedback channel response. A control signal is generated for a pre-distortion circuit to modify the input signal by an inverse of the transmission channel response. The composite system response is measured at a plurality of operating frequencies and at the plurality of offset values. The measurements are stored in a matrix and singular value decomposition is applied to the matrix of measurements to calculate the transmission channel response and feedback channel response.

System and method for estimating a transmit channel response and/or a feedback channel response using frequency shifting

An apparatus is provided. In the apparatus, an input to index (I2I) module maps a complex input into a real signal. A real data tap delay line is coupled to the I2I module and includes N delay-elements. A complex data tap delay line is configured to receive the complex input and includes M delay elements. A set of K of non-linear function modules is also provided. Each non-linear function module from the set has at least one real input, at least one complex input, and at least one complex output. A configurable connectivity crossbar multiplexer couples K of the N real tap delay line elements to real inputs of the set non-linear functions and couples K of the M complex tap delay line elements to complex inputs of the set non-linear function modules.

Systems and methods of power amplifier digital pre-distortion

Systems and methods for transmitting a signal having a desired phase at the device are disclosed. The systems and methods further include determining a signal path length to a device over a transmission line and adding a delay to a signal to be transmitted over the transmission line. The determination is made in response to determining the path length to the device.

Active skew control of a digital phase-lock loop using delay lock-loops

A transceiver for time-domain duplexed (TDD) communications, for example in connection with wireless broadband data communications, is disclosed. The transceiver includes digital predistortion compensation circuitry, which compensates the digital signals to be transmitted based on feedback signals from the output of the power amplifier, in order to linearize the output from the power amplifier. The feedback signals from the power amplifier are coupled back to the digital predistortion circuitry over part of the same receive path as the received signals from the wireless communications channel. The shared path includes analog-to-digital converters that are used both in the transmit period of the TDD cycle to convert the feedback signals from the power amplifier output, and in the receive period of the TDD cycle to convert the analog received signals.

Simplified digital predistortion in a time-domain duplexed transceiver

In one embodiment of the invention, a modulator mixes a transmit-path signal based on a local oscillator (LO) signal and an amplifier amplifies the mixed transmit-path signal to generate an output signal for transmission. A demodulator generates a receive-path signal based on the output signal and the LO signal. Phase-shift control components provide the output signal and the LO signal to the demodulator during a first time duration and provide a phase-shifted version of one of the output signal and the LO signal to the demodulator during a second time duration. The demodulator generates a second receive-path signal based on the one of the phase-shifted output signal and the phase-shifted LO signal during the second time duration. At least one predistortion circuit adjusts at least one of the transmit-path signal and the receive-path signal based on a difference in signal characteristics of the receive-path signal during the second time duration relative to the first time duration.

Growing community of inventors

Rockwall, TX, United States of America

Roland Sperlich