Cadence Design Systems, Inc.

Roland Ruehl

Karun Sharma

Jeffrey Markham

Min Cao

Mathew Koshy

Yinnie Lee

Henry K Yu

Udayan Anand Gumaste

David Allan White

Giles V Powell

Joshua Alexander Baudhuin

Alexandre Arkhipov

Harsh Deshmane

Jeffrey Scott Salowe

Elias Lee Fallon

Eitan Cadouri

Regis R Colwell

Harindranath Parameswaran

Hui Xu

Sanjib Ghosh

Pardeep Juneja

Timothy Rosek

Tianhao Zhang

Anjna Khanna

Simon Simonian

Li-Ling Ma

Krzysztof Antoni Kozminski

Haifang Liao

Arnold Ginetti

Eric Nequist

Frank E Gennari

Ya-Chieh Lai

Gilles S C Lamant

An-Chang Deng

Jonathan R Fales

Xiaojun Wang

Olivier Pribetich

Walter J Ghijsen

Olivier Omedes

Xiaohai Wu

Kenneth Mednick

Saleha Khatun

Yujia Li

Xinming Tu

Tao Hu

Xu Zhu

Mark A Snowden

David Varghese

Wilbur Luo

Srihari Sampath

Various embodiments provide for predicting a simulation result for a circuit design using a machine learning model, which can be used as part of a process of an electronic design automation (EDA) system that measures a circuit design (e.g., timing, power, voltage, current, etc.). In particular, various embodiments described herein can enable modeling simulated time measurements of a circuit design, and can enable such modeling with minimal usage of simulation result data.

Model-based simulation result predictor for circuit design

Various techniques implement an electronic design with hybrid analysis techniques. An activity map is identified or generated for an electronic design. The electronic design is reduced into a reduced electronic design at least by applying a plurality of reduction processes to different portions of the electronic design based in part or in whole upon the activity map. Transient behaviors of the electronic design may be determined or predicted at least by performing one or more transient analyses on a representation of the electronic design with a simulation start point based in part or in whole upon the activity map. The electronic design may then be implemented for manufacturing at least by modifying or correcting the electronic design based at least in part upon the transient behaviors.

Methods, systems, and computer program products for implementing an electronic design with hybrid analysis techniques

Disclosed are techniques for implementing routing aware floorplanning or placement for an electronic design. These techniques preprocess an electronic design and a plurality of inputs for a floorplanner or placer, identify a tentative location for inserting a block comprising one or more pins into a floorplan or placement layout, snap the block to a legal location based at least in part upon one or more characteristics of the one or more pins or one or more pseudo-pins, and update the floorplan or placement layout with one or more geometric routes based in part or in whole upon the legal location.

Method, system, and computer program product for implementing routing aware placement or floor planning for an electronic design

An improved method, system, and computer program product to perform post-layout simulation of an electronic design is provided. According to one approach, a circuit design is divided into multiple partitions for simulation. Simulation is then performed using the established partitions and results are obtained for the different partitions. When any layout editing occurs, identification can be made of any partitions that have been affected by the editing. The affected partitions are re-processed for simulation. The unaffected partitions do not necessarily need to be reprocessed.

Method and system for performing incremental post layout simulation with layout edits

Methods and systems for implementing track pattern for electronic designs are disclosed. The method identifies a first track in a design and viable implementing options for the first track. When adding a second track to the track pattern, the method determines whether the second track corresponds to the viable implementing options for the track. The second track is inserted to the track pattern and situated immediately adjacent to the first track if the second track is determined to correspond to a viable implementing option for the first track. One or more intermediate tracks may be inserted immediately adjacent to the first track before inserting the second track to produce a legal track pattern. Tracks may be removed from a track pattern. One or more intermediate tracks may be inserted into the space occupied by a track being removed to ensure track pattern's compliance with design rules after the track removal.

Method, system, and computer program product for implementing track patterns for electronic circuit designs

Some aspects enable users to interactively define a region in an electronic design, identify or generate a track pattern, and assign the track pattern to the region for subsequent physical implementation for the region. Another aspect interactively represents various results on a display apparatus using one or more distinguishing representation schemes. Another aspect is directed at interactive editing a component of an electronic design having track patterns by iteratively modifying a set of track patterns to reach a reduced set of track patterns and by automatically snapping the component to active track(s) in the reduced set for the physical implementation.

Methods, systems, and articles of manufacture for interactively implementing physical electronic designs with track patterns

Disclosed are techniques for implementing DRC clean multi-patterning process nodes with lateral fills. These techniques identify design rules governing multi-patterning and track patterns by accessing a rule deck to retrieve the design rules, identify a first shape and a second shape sandwiching a space and characteristics of the first and second shapes by examining design data of the electronic design, insert one or more lateral fill shapes in the space by implementing the one or more lateral fill shapes along one or more routing tracks of a legal track pattern while automatically complying with the design rules, and perform post-lateral fill or post-layout operations to improve the layout and to prepare the layout for manufacturing.

Methods, systems, and computer program product for implementing DRC clean multi-patterning process nodes with lateral fills in electronic designs

Disclosed are techniques for implementing parallel fills for bottom-up electronic design implementation flow and track pattern definition for multiple-patterning lithographic processing. These techniques identify a canvas in a layout and design rules for track patterns and multiple-patterning, where the canvas is not yet associated with any base track patterns. A first shape having the first width is inserted along a first track in the canvas based on the design rules. A custom, legal track pattern is generated by arranging multiple tracks in an order and further by associating the first width with the first track in the custom, legal track pattern. The layout may then be further modified by guiding the insertion of one or more additional shapes with the custom, legal track pattern.

Methods, systems, and computer program product for a bottom-up electronic design implementation flow and track pattern definition for multiple-patterning lithographic techniques

Disclosed are techniques for implementing parallel fills for electronic designs These techniques identify a shape and one or more neighboring shapes of the shape by searching design data of a region of a layout of an electronic design, classify the shape and the one or more neighboring shapes by examining respective characteristics of and to categorize the shape and the one or more neighboring shapes into one or more classes, implement one or more parallel fill shapes for at least one shape of the shape and the one or more neighboring shapes by aggregating the one or more parallel fill shapes to the at least one shape based in part or in whole upon the one or more classes while automatically satisfying one or more design rules, and perform one or more post-layout operations on the layout including the one or more parallel fill shapes.

Methods, systems, and computer program product for implementing DRC clean multi-patterning process nodes with parallel fills in electronic designs

Methods and systems for interconnecting circuit components with track patterns are disclosed. The method identifies a source pin on a first track and a destination pin on a second track and determines a third track in a different routing direction based on design rules governing track patterns. The method further determines a transition pattern for the interconnection between the source pin and the destination pin by using at least the third track. The method may use one or more dummy pins or ordering of pin connections in implementing the interconnection to satisfy certain design rules. The lengths of some wire segments of the interconnection may be further adjusted to satisfy certain design rules. Compaction may be performed to have two wire segments share the same track while the lengths or widths of one or both wire segments may be further modified to ensure design rule compliance.

Method, system, and computer program product for interconnecting circuit components with track patterns for electronic circuit designs

Methods and systems for implementing repetitive track patterns for electronic designs are disclosed. The method determines a track pattern within a period and repeats the track pattern for a number of times to form repetitive track patterns. Compliance with photomask designation design rules and track pattern design rules by both the track pattern and the repetitive track patterns is maintained by adding one or more intermediate tracks. A track may be added or removed from the track pattern or replaced by another track associated with a different width by using one or more intermediate tracks. The method may validate a period and replace an invalid period with a valid period. During the identification of the tracks in a track pattern for constructing repetitive track patterns, the method also forward predicts a predetermined number of tracks or predicts one or more tracks for a predetermined distance.

Method, system, and computer program product for implementing repetitive track patterns for electronic circuit designs

Disclosed is a method, system, and computer program product for implementing efficient access to stream data. The present approach implements a stream reader that supports either reading the entire layout (e.g., loading the contents of the user-specified top cell and all its progeny) into memory, or just a portion of it (e.g., loading only the contents of the user-specified top cell and its progeny that overlapped a user-specified bounding box). Some approaches provide a mechanism to implement parallelized or multithreaded reads of the stream data.

Method and system for implementing a stream reader for EDA tools

Disclosed encompasses method, system, computer program product for implementing interactive checking of constraints. Various embodiments bridge schematic design environment and layout environment with a binder mapping process and utilize connectivity information from the schematic design to identify constraint violations early in the physical design stage. The method identifies or creates a layout and identifies or generates an object for a modification process. The method may take snapshot(s) of the design database or may use one or more logs for restoring the design database. The method then identifies or creates scratch pad(s) and performs modification process on the object to generate a change. The method uses scratch pad(s) and trigger(s) to perform constraint checking during the modification process to provide interactive feedback in response to the modification process before committing the change to the persistent database.

Methods, systems, and articles of manufacture for implementing interactive, real-time checking or verification of complex constraints

Systems and methods for real-time design checking of an integrated circuit design, include the operations of receiving at a design tool, design elements of an integrated circuit design entered by an integrated circuit designer; the design tool performing real-time design checks on the design elements as they are entered by the integrated circuit designer to determine whether a design element violates a design rule; when the design tool detects a violation of a design rule based on the design checks alerting the integrated circuit designer; and the design tool presenting a correction to correct the violation of the design rule. The real-time design checks can include, comparing each design element to one or more known non-compliant design elements stored in a database to determine whether a non-compliant design element was entered or is being entered by the integrated circuit designer.

System and method for automated real-time design checking

Growing community of inventors

San Carlos, CA, United States of America

Roland Ruehl