Bull S.a.

Roland Marbot

Reza Nezamzadeh-Moosavi

Andrew Cofler

Jean-Claude Le Bihan

Yves Stricot

Gerard Dehaine

Pascal Couteaux

Jean-Claude Lebihan

Anne Pierre Duplessix

Michel Combes

Michel Moreau

The frequency multiplier 20 is embodied by a phase-locked loop including a phase comparator 11 for commanding a plurality of delay elements 130 to 137 that furnish successive phase-shifted signals CL0-CL7 to a logical adder 16 made up of EXCLUSIVE OR gates.

Phase-locked loop and resulting frequency multiplier

The invention applies to packages for transmitting signals at very high frequencies. A package (10) for the integrated circuit (11) comprises conductors disposed on at least two levels (N1-N6) and distributed so that two pairs of conductors of two fixed potentials (18d, 18g; 19d, 19g), along with a conductor (18s) for single-pole transmission of a signal, form a three-dimensional structure which is approximately coaxial having a characteristic impedance which is substantially constant and predetermined.

Three-dimensional integrated circuit package having conductors at

A process and apparatus for sampling a serial digital signal (D), which includes phasing of the digital signal with a clock signal (C) and sampling the digital signal at delayed instants (Si), wherein the phasing is carried out in reference to the sampling instants. The phasing includes determining phasing test instants (Pi) which refer to the sampling instants (Si) to verify whether transitions of the digital signal are leading or lagging in phase relative to the phasing test instants. The determination of the phasing test instants is achieved by adding to each sampling instant (Si) a delay Y=kR/2, in which k is a positive whole odd number other than zero and R designates a pulse repetition period of the bits of the digital signal (D). The invention has particular utility in data processing and remote data processing systems, and to telecommunication systems.

Apparatus and process for sampling a serial digital signal

The frequency multiplier 10 is embodied by a phase-locked loop including a phase comparator 11 for commanding a plurality of delay elements 130 to 137 that furnish successive phase-shifted signals CL0-CL7 to a logical adder 16 made up of EXCLUSIVE OR gates.

The gates (11) of the exclusive OR type having two inputs (A, B) are disposed in tree structure in successive layers of an integrated circuit beginning with an input layer which receives the input signals of the tree. The output of each gate is connected to an input of a gate in the adjacent layer. Each gate includes two cells (11a, 11b) that switch substantially simultaneously in response to two respective complementary signals (A, NA; B, NB) from one of the two inputs and that supply respective output signals that are representative of the complementary functions (XOR, NXOR) of the exclusive OR type. This makes it possible to obtain propagation times that are perfectly equal whatever the active input of the tree or the edge to be propagation times that are perfectly equal whatever the active input of the tree or the edge to be propagated may be.

Frequency multiplier using XOR/NXOR gates which have equal propagation

An integrated circuit (IC) includes a device (10) that adapts the impedance to the characteristic impedance (Zc) of transmission lines (13) each connecting a transmitter (11) to a receiver (12). Two adaptation blocks (14, 15) reproduce the respective structures of the transmitters (11) and receivers (12) and their impedance is adapted by a reference resistor (Rr). A closed loop control device (Len, Lep, Lrn, Lrp) reproduces the adaptation conditions in the transmitters (11) and receivers (12) respectively.

Impedance adaptation process and device for a transmitter and/or

A method and apparatus for multi-range delay control is disclosed. A method furnishes an output signal (S.sub.K) with a delay that is variable with respect to an input signal (e.sub.0). To enable precise adjustment as a function of a set-point delay (CN) over a plurality of scales, a succession of signals (e.sub.1, e.sub.2, . . . , e.sub.n) delayed with respect to the input signal (e.sub.0) are produced, the delay between a delayed signal (e.sub.2) and the preceding signal (e.sub.1) having a predetermined value. One of the delayed signals (e.sub.2) and a preceding signal (e.sub.1) as selected and a superposition is performed with weighting and an integral effect of the selected signals (e.sub.1, e.sub.2), the selection and weighting being determined as a function of the set-point delay (CN).

Method and apparatus for multi-range delay control

The delay device 10 includes an ECL gate 11, the current source 16 and two resistive load elements 14, 15 of which are associated with an adjusting circuit 23 producing an adjusting voltage Vd, to cause the polarization current of the current source to vary hyperbolically, and a voltage Vh for keeping constant the voltage at the collectors of the transistors 12 and 13 of the gate 11. The delay device 10 causes the delays between the input signals IN, IN* and output signals OUT, OUT* to vary linearly. The invention is applicable in particular to systems for the transmission of digital data at a very high rate, of more than 1 gigabit per second, for example.

Adjustable delay circuit of the current intensity having delay as a

The apparatus for sampling data recurring with a period (R) in the data signal (TS) includes a phasing circuit (43) that adjusts the delay of a clock signal with respect to one edge of the data signal to a value (n+.alpha.) R, where n is a positive integer or 0, and .alpha. is a positive number less than 1. The invention applies in particular to digital data transmission network systems, and in particular to information processing systems.

Data sampling apparatus, and resultant digital data transmission system

The apparatus 15 for serialization of words of N bits SYNC, OP, D0-D7 produces N clock signals CL0-CL9 of period T, delayed successively by T/N, to control respective registers (36, 38, 39) for the successive output of the bits of each word. An adder (40) reunites these bits in a serial data transmission signal (TS). The deserialization is applicable in particular to network transmission systems, and especially to information processing systems.

Apparatus for serialization and deserialization of data, and resultant

In certain bidirectional transmissions, differential links (L, L*) are used and transceivers (1) that furnish differential measurement signals (V, V*) representative of the transmission signals of the remote station are used. To reduce power consumption, the electrical power to the transceivers (1) may be interrupted during periods of inactivity. The method of the present invention consists in determining a threshold value which is intermediate in value between the maximum and minimum values that can be assumed by the measurement signals (V, V*), and furnishing a signal (VAL) representative of transmission activity resulting from the comparison between the measurement signals (V, V*) and the threshold value. The circuit for employing the method uses voltage comparators and may be an integrated circuit.

Process and circuit for detecting transmission using bi-directional

The invention relates to tests for verifying the integrity of circuits (16) for serial bi-directional transmissions. These tests are capable of testing transceivers (12) operating a very high frequency without creating interference and consist in either leaving the serial output of the transceiver (12) disconnected from the line (L), or disconnecting (INF) its adaptation impedance, commanding the transmission of signals, and comparing the signals transmitted to the reception signals detected by the same transceiver. In a variant, the adaptation impedance of the transceiver of the remote station may be disconnected.

Processes for testing bi-directional serial transmissions, and circuits

The invention relates to an integrated circuit including impedances having precise values. To compensate for process variations and drift in impedances, the circuit includes automatic control means (3) to adjust the value of impedances (R) to a value that is a function of that of a reference impedance (Rc) external to the integrated circuit.

Integrated circuit having controller impedances and application to

Transceiver for transmission over serial bi-directional links having a bi-directional amplifier including an impedance (R) for adaptation to the line and connected to it, a generator (G1) commanded for transmission and supplying the adaptation impedance (R) and the line in parallel, detection device (G2, r) for furnishing a measurement signal (V) representative of either the current circulating in the adaptation impedance (R) when the generator (G1) is active, or the sum of the current in the adaptation impedance (R) and a compensation value when the first generator (G1) is not active. The compensation value is determined so as to make the measurement signal (V) independent of the transmission state of the transceiver.

Transceiver for bidirectional link, integrated circuit including the

The variable delay device 10 includes an ECL gate 11 associated with an adjusting circuit 23 acting on the resistance of resistive load elements 14, 15 of transistors 12, 13 and the resistive load element 18 of the current source 16 at the gate 11 to cause the current produced by the source 16 to vary linearly while keeping the voltage at the collectors of the transistors 12, 13 constant. The range of variation of the resistances is selected in such a way that the delay between the input signals IN, IN* and OUT, OUT* varies substantially linearly. The invention is particularly applicable to systems for digital data transmission at a very high rate, of more than 1 gigabit per second.

Growing community of inventors

Versailles, France

Roland Marbot