Xerox Corporation

Trw Limited

Roland J Handy

Jagdish C Tandon

Abd-el-Fattah A Ibrahim

Narayan K Kadekodi

James C Stoffel

Thomas A Zimmerman

A high density charge coupled device imaging array 88 with a bilinear array of photosites on a single integrated circuit chip is utilized in an image scanning configuration. Offset photosites 90a, 94a in the two separated rows are coupled via transfer gates 98, 106 to storage registers 104, 108 and then to two shift registers 110, 112, and via transfer gates 96 directly to two shift registers 100, 102 in a quadrilinear array. The output of these four shift registers 110,102,110,112 are multiplexed to generate a single output pulse train representative of the information scanned. By separating the offset rows 90, 94 of photosites by a row 92 therebetween, the necessity for accurate alignment of the photosite areas is reduced.

High density CCD imager

A charge coupled device (CCD) amplifier is utilized for amplification of charge packets as small as 500 electrons into usable signals. Very little noise is injected into the signal. The charge amplifier consists of two connecting electrodes, one designated as the detector G.sub.1 and the other designated as the response G.sub.2, physically separated by any convenient distance on the same LSI chip surface on which an NMOS field effect transistor (FET) is attached. Also coupled to the FET is another electrode G.sub.3 designated as the amplifier gate. The charge amplifier structure is embedded in the silicon dioxide layer, with the detector response, and amplifier electrode being located some convenient distance above the silicon-silicon dioxide interface.

High dynamic range charge amplifier

A unique charge coupled device imager is utilized to provide high density, large dynamic range recording, with fast response time by injecting the photoelectric detected charge directly from the photosite area to the output shift register. In essence, therefore, the area beneath the photosite used for storage of the injected charge is, in fact, the output shift register, in real time.

High dynamic range CCD detector/imager

A high density charge coupled device imaging array 58 with a bilinear array 60, 62 of photosites on a single integrated circuit chip is utilized in an image scanning configuration. Offset photosites 60a, 62a in two rows are coupled via transfer gates 64 to storage register 72 and then to two shift registers 74, 76, and via transfer gates 66 directly to two shift registers 68, 70 in a quadrilinear array. The output of these four shift registers 68, 70, 74, 76 are multiplexed to generate a single output pulse train representative of the information scanned.

High resolution imager employing staggered sensor structure

Utilizing a plurality of analog to digital converter cells with transfer gates as implemented by large scale integrated circuit techniques incorporating charge coupled device technology, a 16 bit or larger analog to digital converter is achieved. On a single integrated circuit chip, the necessary A/D cells are formed, whereby in each cell gate and charge packet transfer paths allow for the analog to digital conversion. With transfer gates coupling the A/D cells, the multi-bit A/D conversion register is constructed. Digital voltage levels indicative of logic 0's or logic 1's are generated from varying analog charge levels applied.

16 Bit analog to digital converter

An analog to digital converter as implemented by large scale integrated circuit techniques utilizing charge coupled device technology. On a single integrated circuit chip, the necessary gate and charge packet transfer paths are formed to allow for the analog to digital conversion. Depending on the amount of charge transferred from one location to the next the two outputs will denote a digital voltage level indicative of logic 0 or logic 1.

CCD Analog to digital converter

A logic gate utilizing charge transfer structures is disclosed which forms the building block for a TWO (2)-INPUT ADDER (HALF ADDER) and a THREE (3)-INPUT ADDER (FULL ADDER). The logic gate includes a first storage gate for receiving charge packets representing binary digital input signals. The storage gate couples in a first path to a first transfer gate which allows the storage gate to store only one unit quantity Q of charge and to transfer any excess quantity of charge to a master gate. The master gate is connected to a slave gate which causes the latter to operate as a barrier gate when the master gate contains a unit quantity Q of charge or to operate as a transfer gate when the master gate contains no charge. A control gate couples the first storage gate in a second path to the slave gate. The control gate exercises control over the transfer of charge in the second path until such time as the master gate can receive and store the excess charge from the first storage gate and thereby determine the appropriate state of the slave gate before the second path is allowed to transfer charge from the first storage gate.

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Northridge, CA, United States of America

Roland J Handy