Micron Technology Incorporated

Roland J Awusie

Andrew Bicksler

Deepak Thimmegowda

Kishore Kumar Muchherla

Harish Reddy Singidi

Jung Sheng Hoei

Michael G Miller

Renato C Padilla

Gary F Besinga

Sampath K Ratnam

Ashutosh Malshe

Gianni Stephen Alsasua

Peng Fei

A first pool of blocks of a memory device is determined, wherein blocks of the first pool are associated with storing system data at a single bit per memory cell. A second pool of blocks of the memory device is determined, wherein blocks of the second pool are associated with storing user data at a plurality of bits per memory cell. In response to detecting a failure associated with a particular block of the second pool of blocks, the particular block is added to the first pool of blocks.

Bad block management for memory sub-systems

Some embodiments include a transistor having a first electrically conductive gate portion along a first segment of a channel region and a second electrically conductive gate portion along a second segment of the channel region. The second electrically conductive gate portion is a different composition than the first electrically conductive gate portion. Some embodiments include a method of forming a semiconductor construction. First semiconductor material and metal-containing material are formed over a NAND string. An opening is formed through the metal-containing material and the first semiconductor material, and is lined with gate dielectric. Second semiconductor material is provided within the opening to form a channel region of a transistor. The transistor is a select device electrically coupled to the NAND string.

Transistors, semiconductor constructions, and methods of forming semiconductor constructions

A processing device in a memory system performs operations comprising determining a first pool of data blocks of the memory device, wherein data blocks of the first pool are associated with storing data at a first number of bits per memory cell; determining a second pool of data blocks of the memory device, wherein data blocks of the second pool are associated with storing data at a second number of bits per memory cell that is larger than the first number of bits per memory cell; detecting a failure associated with a particular data block of the second pool of data blocks; and in response to detecting the failure associated with the particular data block, removing the particular data block from the second pool of data blocks and adding the particular data block to the first pool of data blocks.

A memory device comprising a main memory and a controller operably connected to the main memory is provided. The main memory can comprise a plurality of memory addresses, each corresponding to a single one of a plurality of word lines. Each memory address can be included in a tracked subset of the plurality of memory addresses. Each tracked subset can include memory addresses corresponding to more than one of the plurality of word lines. The controller is configured to track a number of read operations for each tracked subset, and to scan, in response to the number of read operations for a first tracked subset exceeding a first threshold value, a portion of data corresponding to each word line of the first tracked subset to determine an error count corresponding to each word line of the first tracked subset.

Memory devices and methods for read disturb mitigation involving word line scans to detect localized read disturb effects and to determine error count in tracked sub sets of memory addresses

A first group of data blocks of a memory sub-system is determined. The first group of data blocks is associated with a failure condition. Also, a second group of data blocks of the memory sub-system is determined. The second group of data blocks is not associated with the failure condition. User data is received and system data of the memory sub-system that is associated with the user data is generated. The system data is stored at the first group of data blocks that is associated with the failure condition by using a first programming operation. The user data is stored at the second group of data blocks that is not associated with the failure condition by using a second programming operation. The second programming operation is different from the first programming operation.

Several embodiments of memory devices and systems with read level calibration are disclosed herein. In one embodiment, a memory device includes a controller operably coupled to a main memory having at least one memory region and calibration circuitry. The calibration circuitry is operably coupled to the at least one memory region and is configured to determine a read level offset value corresponding to a read level signal of the at least one memory region. In some embodiments, the calibration circuitry is configured to obtain the read level offset value internal to the main memory. The calibration circuitry is further configured to output the read level offset value to the controller.

Memory devices with read level calibration

Semiconductor constructions which include metal-containing gate portions and semiconductor-containing gate portions

A memory device comprising a main memory and a controller operably connected to the main memory. The main memory can comprise a plurality of memory addresses, each corresponding to a single one of a plurality of word lines. Each memory address can be included in a tracked subset of the plurality of memory addresses. Each tracked subset can include memory addresses corresponding to more than one of the plurality of word lines. The controller is configured to track a number of read operations for each tracked subset, and to scan, in response to the number of read operations for a first tracked subset exceeding a first threshold value, a portion of data corresponding to each word line of the first tracked subset to determine an error count corresponding to each word line of the first tracked subset.

Growing community of inventors

Boise, ID, United States of America

Roland J Awusie