Infineon Technologies Ag

Roland Haberkern

Georg Tempel

Roman Knoefler

Stephan Riedel

Veronika Polei

Elard Stein Von Kamienski

The method aims at improving the charge confinement of the memory layer at the edges facing the regions of buried bitlines. After the deposition of the memory layer between confinement layers and the implantation of dopants for bitlines and source/drain regions, an oxidation of semiconductor material to form upper bitline isolation regions takes place. By this method, additional oxide regions are produced at the edges of the memory layer in the same oxidation step. Either a silicon layer may be deposited and reduced to sidewall spacers, which are subsequently oxidized; or recesses are etched into the memory layer and subsequently filled with semiconductor oxide.

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Dresden, Germany

Roland Haberkern