International Business Machines Corporation

Roland Chanclou

Patrick Mone

Myriam Combes

Carl Cederbaum

Vincent Vallet

Bernard Auda

A semiconductor structure for making four device SRAMs with stacked polysilicon load resistors (4D/2R SRAM cells) in CMOS FET technology. The structure is formed from a semiconductor substrate with active regions of devices therein and polysilicon lines formed thereupon. A first thick passivating layer is formed of an etch stop layer and a layer of phosphosilicate glass (PSG) above the substrate. A set of first metal contact studs through the first thick passivating layer contacts at least one of the active regions and/or the polysilicon lines. The etch stop layer (26) may be of intrinsic polysilicon or Al.sub.2 O.sub.3. The top surface of the first contact studs is coplanar with the top surface of the first thick passivating layers. A plurality of polysilicon lands formed on the planar structure contact the first contact studs. The polysilicon lands are highly resistive, highly conductive or a mix thereof. A second thick passivating layer is formed above the resulting structure having a set of second metal contact studs therein. The second metal studs contact at least one of the polysilicon lands and/or one of the first contact studs. The top surface of the second contact studs is coplanar with the top surface of the second thick passivating layer. A plurality of metal lands is formed above the second thick passivating layer and in contact with the second contact studs. A final insulating film insulates and passivates the metal lands.

Stacked conductive resistive polysilicon lands in multilevel

A method of forming thin film pseudo-planar polysilicon gate PFETs (pPFETs) simultaneously with bulk PFET and NFET devices in a CMOS or BiCMOS semiconductor structure, comprising the steps of: providing a P-type silicon substrate having a surface that includes a plurality of isolation regions; delineating polysilicon lands at selected isolation regions; forming N-well regions into the substrate at a location where bulk PFETs are to be subsequently formed; forming insulator encapsulated conductive polysilicon studs to provide gate electrodes at desired locations of the structure; forming self-aligned source/drain regions of the bulk NFETs into the substrate; forming self-aligned source/drain regions of the bulk PFETs and pPFETs into the substrate and into the polysilicon lands, respectively; and forming contact regions to the selected locations that include the source/drain regions. In particular, the method finds application in the formation of polysilicon PFETs which are extensively used as load devices in six device (6D) SRAM cells.

Method of forming thin film pseudo-planar FET devices and structures

A semiconductor structure including: a semiconductor substrate (18/19) having active regions (21) of devices (T1, . . . ) therein and/or polysilicon lines (23-1, . . .) formed thereupon; a first thick passivating layer (26/27) formed above the substrate having a set of first metal contact studs (30-1, . . .) therein contacting at least one of the active regions (21) and/or the polysilicon lines (23-1, . . . ); the surface of the first contact studs is coplanar with the surface of the first passivating layer; a plurality of polysilicon lands (31-1, . . .) formed on the planar structure in contact with the first contact studs; the polysilicon lands are either highly resistive, highly conductive or a mix thereof; a second thick passivating layer (34/35) formed above the resulting structure having a set of second metal contact-studs (37-1 . . .) therein contacting at least one of the polysilicon lands and/or one of the first contact studs; the surface of the second contact studs is coplanar with the surface of the second thick passivating layer. a plurality of metal lands (38-1, . . . ) formed above the second thick passivating layer (34/35) in contact with the second contact studs; a final insulating film (39). The structure of the present invention may be advantageously used in chips implementing four device SRAM cells with stacked polysilicon load resistors (4D/2R SRAM cells) in CMOS FET technology. The present invention also relates to the method for fabricating the same.

Method of forming stacked conductive and/or resistive polysilicon lands

A follow-up system for monitoring the etching process in RIE equipment. A spectrometer is used in an interferometric mode for accurate thickness measuring to produce high-resolution and reproducible patterns in a layer of etchable material formed on a substrate.

Follow-up system for etch process monitoring

A manufacturing method is provided for producing a stacked semiconductor structure including: depositing a first thick passivating layer onto the base structure; forming first stud openings in the first thick passivating layer exposing at least one active region and/or one of the polysilicon lines; depositing a first layer of a conductive material to fill the first stud openings and define first contact studs, the upper part of some of the first contact studs comprising the gate electrodes of PFET devices; planarizing the structure to make the top surface of the first contact studs coplanar with the surface of the first thick passivating layer; depositing a thick insulating layer to form the gate dielectric of PFET devices and patterning it to define contact openings to expose selected first contact studs at desired locations; depositing a layer of polysilicon; patterning the polysilicon layer to define polysilicon lands containing the first contact studs at the desired locations; selectively implanting to define the source and drain regions of the PFET devices and interconnection conductors; depositing a cap layer; depositing a second thick passivating layer forming second stud openings in the second thick passivating layer to expose desired portions of the polysilicon lands and/or portions of the first contact studs; depositing a second layer of conductive material to define second contact studs; and planarizing the structure to make the top surface of the second contact studs coplanar with the surface of the second thick passivating layer.

Method of forming stacked tungsten gate PFET devices and structures

A stacked semiconductor structure including a base structure (18/19) is comprised of a semiconductor substrate having active regions (21) of devices (N1, . . . ) formed therein and/or a plurality of polysilicon lines (23-1, . . . ) formed thereupon; a first thick passivating layer (26/27) having a set of first metal contact studs (30-1, . . . ) therein contacting at least one of said active regions (21) and/or said polysilicon lines (23-1, . . . ), the surface of said first metal contact studs being coplanar with the surface of said first thick passivating layer; a plurality of first polysilicon lands (31-1, . . . ) formed on the said thick passivating layer, certain portions of said first polysilicon lands defining the source, drain and channel regions forming the body of a PFET device with at least one region (SP1) contacting one of said first metal contact studs; a thin insulating layer (33) forming the gate dielectric layer of said PFET device; a plurality of highly doped second polysilicon lands (35-1A, . . . ) formed over by said thin insulating layer (33); a certain portion of said second polysilicon lands (35-1A, . . . ) forming the gate electrode (GP1) of said PFET device (SP1) which is self-aligned with said source (SP1) and drain (DP1) regions; a second thick passivating layer (37/38) having a set of second metal contact studs (40-1, . . . ) therein contacting at least one of said first or second polysilicon lands (31-1, . . . ; 35-1, . . . ) and/or said first contact studs (30-1, . . . ); the surface of said second metal contact studs is coplanar with the surface of said second thick passivating layer; a first metal interconnection configuration having metal lands (41-1, . . . ) electrically contacting at least one of said second metal contact studs (40-1, . . . ); and, a final insulating film (42).

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Perthes, France

Roland Chanclou