Texas Instruments Corporation

Roland Bucksch

Nigel Peter Smith

Sameer P Pendharkar

Amitava Chatterjee

Erich Bayer

Jozef C Mitros

Philipp Steinmann

Lily Springer

Nicola Rasera

Stefan Reithmaier

Ivan Shumkov

Doug Weiser

William E Grose

Maciej Piotr Jankowski

Reed Wilburn Adams

Siva Srinivas Kothamasu

Kazunobu Shin

Christian Rott

Florian Neveu

James John Doublesin

Examples of circuitry and systems and methods provide a multi-way configurable amplifier to support various applications. The multi-way configurable amplifier may include a reconfigurable filter that comprises first and second inputs adapted to receive an input signal; a fully differential amplifier (FDA); and first and second reconfigurable resistance-capacitance (RC) networks. The FDA has an inverting input, a non-inverting input, an inverting output, and a non-inverting output. The inverting input is coupled to the first input, and the non-inverting input is coupled to the second input. The first reconfigurable RC network is coupled to the non-inverting output, and the second reconfigurable RC network is selectively couplable to the inverting output. The reconfigurable filter is configurable to enable operation in any of multiple modes including a single-ended mode of operation and a differential mode of operation.

Isolated amplifiers with reconfigurable filter

In an example, a dual-phase inverting buck-boost power converter for use with at least first and second energy storage elements includes an inverting buck-boost power converter and an inverting boost converter. In an example, the inverting buck-boost power converter is coupled between an input node and an output node of the dual-phase inverting buck-boost power converter and includes a first plurality of switches operable to couple to the first energy storage element, wherein the inverting buck-boost power converter is operable to supply a first load current. In an example, the inverting boost converter is coupled in parallel with the inverting buck-boost power converter between the input node and the output node of the dual-phase inverting buck-boost power converter and includes a second plurality of switches operable to couple to the first and the second energy storage elements, wherein the inverting boost converter is operable to supply a second load current.

Inverting buck-boost power converter

A programmable level shifter for providing upshifted control signals to an active matrix display based on logic-level control signals received from a timing controller. The programmable level shifter includes a programmable state machine, level-shifting output drivers, and a programming interface. The programmable state machine is configured to receive at least one control signal from a timing controller. The state machine generates, based on said at least one control signal, a plurality of outputs for driving gate drivers of the active matrix display. The level-shifting output drivers convert the plurality of outputs generated by the programmable state machine to a higher-magnitude voltage level. The programming interface facilitates the programming of aspects of the programmable state machine.

Programmable level shifter for LCD systems

A system having multiple power mode types, for example, includes a power manager that is responsive to a selection of a suspend power mode type for maintaining processor context information in volatile memory while the processor is in the selected suspend mode. A status register is arranged to retain the status of the context information in the volatile memory while the processor is in the selected suspend power mode. The power manager is arranged to selectively apply power to various voltage domains in response to the type of power mode selected. The processor is optionally arranged to signal the power manager of transitions to the selected suspend mode and of transitions to an active mode using a power enable signal.

Valid context status retention in processor power mode management

A method is presented, in which a thin film resistor is modeled to account for self-heating. The method includes fabricating the thin film resistor and characterizing a thermal resistance of the thin film resistor, wherein the thermal resistance accounts for self-heating thereof during operation. The thermal resistance is then used in a model for simulating integrated circuits using the thin film resistor.

Modeling process for integrated circuit film resistors

Disclosed are devices and associated methods for manufacturing an EEPROM memory cell ( ) for use on a negatively biased substrate ( ). The invention may be practiced using standard semiconductor processing techniques. Devices and methods are disclosed for a floating gate transistor for use as an EEPROM cell ( ) including a DNwell ( ) formed on a P-type substrate ( ) for isolating the EEPROM cell ( ) from the underlying P-type substrate ( ).

Single-poly EEPROM on a negatively biased substrate

An EEPROM ( ) comprises a source region ( ), a drain region ( ); and a polysilicon layer ( ). The polysilicon layer ( ) comprises a floating gate comprising at least one polysilicon finger ( A- E) operatively coupling the source region ( ) and drain region ( ) and a control gate comprising at least one of the polysilicon fingers ( A- E) capacitively coupled to the floating gate. The EEPROM ( ) has a substantially reduce area compared to prior art EEPROM since an n-well region is eliminated.

Single poly EEPROM with reduced area

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Buch am Erlbach, Germany

Roland Bucksch