Qimonda Ag

Infineon Technologies Ag

Bayerische Motoren Werke Aktiengesellschaft

Other

Qimonda

Roland Barth

Peter Gregorius

Hermann Ruckerbauer

Johannes Stecker

Dirk Scheideler

Christoph Bilger

Maurizio Skerlj

Michael Bruennert

Wolfgang Walthes

Alexander Benedix

Reinhard D&uuml;regger

Stephan Grosse

Robert Hermann

Reinhard Dueregger

Wolfgang Kreinhoefner

Klaus Mayinger

A system including a central processing unit, a first memory channel being configured to couple the central processing unit to a first semiconductor memory unit, wherein the first memory channel is configured to be clocked with a first clock frequency, and a second memory channel being configured to couple the central processing unit to a second semiconductor memory unit, wherein the second memory channel is configured or configurable to be clocked with a second clock frequency smaller than the first clock frequency.

Memory system with extended memory density capability

The invention provides a method and an apparatus for determining a skew of each data bit of an encoded data word received by a receiver via an interface from a transmitter comprising the steps of performing an error check and correction of the received and sampled encoded data word to calculate an error corrected encoded data word corresponding to the encoded data word transmitted by the transmitter, and correlating a sequence of error corrected encoded data words with the sampled encoded data words to determine a skew of each data bit of said received encoded data words.

Method and apparatus for determining a skew

The multi-die memory comprises a first die and a second die. The first die comprises a first group of memory banks, and the second die comprises a second group of memory banks. The first group of memory banks and the second group of memory banks are coupled to a common memory interface. The common memory interface couples the multi-die memory with an internal connection.

Multi-die memory, apparatus and multi-die memory stack

The invention provides a memory circuit comprising a plurality of storage cells for storing data and redundant spare storage cells for replacing defective storage cells, and a memory access logic for accessing said storage cells connected to a replacement setting register which is writeable during operation of said memory circuit to store replacement settings.

Memory circuit

An integrated circuit includes a device stack including: a memory device with a first wireless coupling element, and a semiconductor device with a second wireless coupling element. The first and second wireless coupling elements are arranged face-to-face and are configured to provide a wireless connection between the memory device and the semiconductor device.

Integrated circuit with wireless connection

Method and apparatus that relate to a storage device comprising a plurality of memory cells, an interface device configured to connect the storage device to a host system and configured to transmit signals to read and write data from the host system to the memory cells via a first and second data path, and a logic unit. The logic unit is configured to read and write data from the plurality of memory cells via the second data path, and configured to perform logic operations on data stored in the plurality of memory cells. When performing read and write operations, the first data path excludes the logic unit, and the second data path includes the logic unit. Furthermore, the logic unit is communicatively coupled between the interface device and the plurality of memory cells. Additionally, a method for manufacturing the memory device is provided.

Method and apparatus for storage device with a logic unit and method for manufacturing same

An integrated semiconductor memory device includes a clock terminal that applies an external clock signal. Read and write accesses are controlled synchronously with the external clock signal. A frequency detector is connected to the clock terminal to detect the frequency of the external clock signal. The frequency detector circuit generates a control signal in a manner dependent on the frequency of the external clock signal, the control signal being used to drive a controllable voltage generator, which generates a level of an internal supply voltage in a manner dependent on the control signal, from which supply voltage further control and supply voltages are derived. The integrated semiconductor memory device makes it possible to adapt the level of internally generated voltages of the integrated semiconductor memory device to the frequency of the external clock signal.

Integrated semiconductor memory devices with generation of voltages

A temperature sensor is integrated together with an integrated circuit on a chip, the sensor delivering a temperature-dependent measuring signal or at least emitting a signal when the chip temperature falls below a specific prescribed value. For such an eventuality, the chip includes a special circuit device thereon, by which a current flow is generated through a provided structure of electrical conductors that keeps the temperature of the integrated circuit above a prescribed minimum temperature.

Integrated circuit with temperature sensor and method for heating the circuit

A dynamic semiconductor memory and a method for operating such a memory includes memory banks with memory cells disposed in rows, and registers associated with the memory banks for storing an address of an open, activated word line. In the event of an external refresh command, a control device causes, after the refresh operation, the state of the memory banks to be reestablished, in particular, the word line whose address was stored in the register to be reactivated. Such a purely on-chip measure increases the operating speed of the memory.

Dynamic semiconductor memory with refresh and method for operating such a memory

A semiconductor configuration is described and has a temperature sensor, which measures a temperature of a semiconductor module. The measured temperature is provided to a control unit, so that the control unit can adapt a refresh cycle in the semiconductor module to the retention time corresponding to the measured temperature.

Semiconductor configuration with optimized refresh cycle

An arrangement for the relative adjustment of the angle of rotation of a shaft with respect to a driving wheel, particularly a control shaft of an internal-combustion engine, in which a device for frictional damping equipped with a prestressed diaphragm spring is provided between the driving wheel and the shaft. For achieving a frictional damping which does not abate in the case of operationally caused component changes, the diaphragm spring is selected with a course of the characteristic curve which is relatively negative in sections. The diaphragm spring is prestressed such that a spring path is assigned to the diaphragm spring along a predetermined operating range in the relatively negative course of the characteristic curve.

Arrangement for relative adjustment of rotation angle of a control shaft of an internal combustion engine

In a method for operating a hydraulically controlled/regulated camshaft adjuster for internal combustion engines, in which a mechanical adjusting device designed to retard the camshaft is controlled by a piston that is hydraulically chargeable on at least one side, to which piston a pressure medium from a hydraulic circuit with a separately driven pump is supplied to an accumulator and to a valve controlled as a function of the operating point, in order to reduce harmful exhaust components when the engine starts, when the engine starts, pressure medium is supplied to the piston from an essentially full accumulator as a function of a start signal under valve control in order to advance the camshaft using the adjusting device.

Growing community of inventors

Munich, Germany

Roland Barth