International Business Machines Corporation

Roland A Bechade

Clarence Rosser Ogilvie

Frank David Ferraiolo

Stephen Gerard Shuma

Steven Frederick Oakland

Martin Stanley Schmookler

Ilya I Novof

Kenneth J Shaw

Leon Skarshinski

Bruce A Kauffmann

Charles R London

Bruce Kaufmann

Bruce A Kaffmann

Bruce A Kauffman

Robert Hayosh

William K Hoffman

A carry select adder including a two level carry selector connected to multiple carry chains. Two or more adders produce at least two pairs of candidate carry-out signals in parallel. For each pair, a first candidate carry-out signal is based on a first presumed carry-in signal and a second candidate carry-out signal is based on a second presumed carry-in signal different than the first presumed carry-in signal. A two-level selector for simultaneously selects, for each of the pairs of candidate carry-out signals, either the first candidate carry-out signal or the second candidate carry-out signal as an actual carry-out signal, based on an actual carry-in signal. Both selected carry out signals are passed to.

Carry select adder using two level selectors

A carry select adder includes an adder for outputting a first sum of values based on a first presumed carry-in of zero and a second sum of the values based on a second presumed carry-in of one. A sum unit produces an actual sum comprising either the first sum or the second sum based on an actual carry-in and simultaneously determines whether the actual sum is all zeros or all ones. The sum unit selects the actual sum and determines whether the actual sum comprises all zeros or ones in the same time period such that there is no significant additional delay associated with the zero/one detection operation.

Zero and one detection chain for a carry select adder

By combining a count leading zero circuit with a bit shifter in a digital processor though detection of groups of leading zeros prior to completion of counting of leading zeros, shifting for normalization and number format conversion can concurrently be initiated and partially carried out prior to completion of a determination of the number of leading zeros in an expression of a number. The combined count leading zero circuit and shifter provides faster operation which can be completed within one cycle time and hardware architecture simplifications are achieved to reduce required circuit element count and chip space.

Optimized, combined leading zeros counter and shifter

An apparatus and method for comparing values A comparator comprising inputting two comparison values to be compared, determining the number of a leading '1' in each of the values and outputting two position values, wherein the position values have a bit size smaller than the comparison values, comparing a first position value of the position values from a second position value of the position values, and outputting a signal indicating a first comparison value of the comparison values is either greater than a second comparison value of the comparison values, equal to the second comparison value or less than the comparison value, based on a result of the comparing operation.

N-bit comparator using count leading 1 circuits

In connection with a logic circuit including a mask generator for determining a value for a so-called 'sticky bit' in a binary number to be truncated and rounded, an intermediate signal is taken from the mask generator and an Exclusive-OR function applied to adjacent bits to generate a second mask containing or adjacent to a transition between the portion of the number to be dropped and the portion to be retained in the truncated number. The second mask is applied to different overlapping groups of bits in a portion of the number which contains the least significant bit and the guard bit as determined from the number of bits to be dropped, for example, by shifting out from a shifter, as the number is truncated and rounded to extract a specific bit in each group of bits. By extracting such specific bits using a mask, the extraction process is removed from the critical path of the processor which includes the shifter and the extraction process can proceed in parallel with the shifting process.

Least significant bit and guard bit extractor

A fast 4-2 carry save adder using multiplexers and inverters only, for receiving four one bit data inputs and a one bit carry-in, and generating a sum and a carry-dependent output in three logic delays and a carry-independent carry out in two logic delays. The 4-2 carry adder has particular application in multiplier arrays.

Fast 4-2 carry save adder using multiplexer logic

Signal propagation time through a transmission gate array or multiplexer is significantly reduced and output signal transition time is halved by detecting non-selection of a section of the multiplexer and activating an output circuit, preferably in the form of a logic gate, to respond to a signal passed through a selected section of the transmission gate array or multiplexer. Specifically, upon non-selection of a section, an appropriate logic-valued signal at a reference voltage is propagated on an internal node of the multiplexer to the input of the output circuit to precondition or activate the output circuit. Since this signal is strongly tied to the reference voltage, the response of the output circuit is improved in both response time and transition time. Further, capacitance of internal nodes of the multiplexer is insulated or isolated from the inputs to the multiplexer, avoiding trade-offs between circuit performance and wiring congestion.

Distributed multiplexer

A high speed apparatus and method for determining the number of leading zeros or ones in a binary data field, in particular, a fixed-sized field, and further, indicating whether all of the bits of the binary data field are zero or one, is provided. The apparatus includes a plurality of detector circuits, coupled in parallel, to input different sections of the binary data field. For a leading zero detection operation, each detector circuit is configured to identify the bit location which contains the most significant '1' of the section of the binary data field which the detector inputs, and output a binary number signal representing the number of zeros leading that most significant '1'. Each detector circuit also determines whether each bit location in the section which the detector inputs contains a '0' and provides a zero-detect signal representing this condition. The binary number signals and zero detect signals are provided to decoder circuitry and a plurality of multiplexor circuits which cooperate, based on these signals, to output a binary number signal representing the number of leading zeros in the entire binary field, and a zero detect signal indicating whether every bit location in the entire binary field contains a '0'. The binary number signal representing the number of leading zeros in the entire binary field can then be provided to shifting circuitry to shift the binary field as desired to normalize the binary field.

Method and apparatus for determining the amount of leading zeros or ones

A method and circuit for store rounding a number wherein the guard bit and least significant bit of the number are selectively exchanged depending on the IEEE rounding mode to simplify the decision-making circuit. Zero detection logic is performed on the guard, round and sticky bit positions to determine if incrementing is required. An incrementer provided with the number and a guard bit, which may be the true guard bit or a predetermined constant value depending on the rounding mode, responds to the zero detection logic to increment the number from the guard bit position.

Method for store rounding and circuit therefor

A structure for and method of operating a transition-controlled off-chip driver is disclosed. Turn-on of output pulling devices is controlled, while turn-off is uncontrolled. An AC voltage reference circuit dissipating essentially zero DC power provides a reference voltage for control during transition. Turn-on control dissipates during transition, and ends when transition is complete without the use of output feedback.

Transition-controlled off-chip driver

A multiplication circuit for a floating point digital processing system includes a partial products generator and a carry adder circuit for determining a product resulting from multiplication of an M bit multiplicand and an N bit multiplier. The partial products generator outputs to the carry adder circuit partial products based on the M bit multiplicand and N bit multiplier. The carry adder circuit contains a plurality of carry adders connected in a hierarchical tree structure such that a plurality of carry adder stages are defined, with each carry adder stage except a first carry adder stage receiving adder sums from a next adjacent, lower carry adder stage in the hierarchical tree structure. The first carry adder stage receives the partial products output from the partial products generator. The multiplication circuit is optimized by employing carry select adders or carry look-ahead adders in the hierarchical tree structure.

Multiplier employing carry select or carry look-ahead adders in

A process independent digital clock shaping network is described for generating an internal clock signal having preset high state (T.sub.on) and low state (T.sub.off) intervals per cycle from a received clock signal having a substantially constant period but variable T.sub.on and T.sub.off intervals per cycle. The shaping network utilizes a set/reset latch to output the desired clock signal. The set input to the latch receives a set pulse generated at the beginning of each cycle of the received clock signal and the reset input to the latch receives a reset pulse generated by control logic circuitry. The logic circuitry uses the frequency of the received clock signal to generate a reset pulse at the appropriate time for gating of the latch to produce an output clock signal having the desired T.sub.on and T.sub.off intervals per cycle.

Process independent digital clock signal shaping network

A process independent digital clock signal timing network is described for generating a chip clock substantially in phase with and offset by one cycle from an input clock signal. The timing network determines the delay experienced by a clock signal passing through a predetermined internal clock circuit on the chip and pregates the internal clock circuit by an amount equivalent to the determined delay such that the chip clock signal output from the internal clock circuitry lags the external clock signal input to the semiconductor chip by one cycle. Various timing network embodiments are described and claimed.

Clock signal latency elimination network

A logic synthesis network for efficiently combining respective bit pairs of first and second operands to produce respective sum bits and a carry bit associated with the most significant sum bit. A dummy generator receives the respective bit pairs and generates first and second dummy sum signals, and first and second pairs of dummy carry signals. A first dummy selector chain selects the appropriate dummy sum and carry signals of all the bits other than the least significant bit, as a function of the state of the first pair of dummy carry signals generated for the least significant bit pair. A second dummy select chain selects the appropriate dummy sum and carry signals for all the bit pairs other than the least significant bit pair, as a function of the state of the second pair of dummy carry signals generated for the least significant bit pair. Sum generators associated with each bit choose between the selected dummy sum signals from the first and second dummy select chains in accordance with the state of the carry-in signal associated with the least significant bit pair. Carry generators associated with each bit pair choose between the first and second pairs of dummy carry signals at the ends of the first and second dummy select chains, again in accordance with the state of the carry-in signal associated with the least significant bit pair.

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South Burlington, VT, United States of America

Roland A Bechade