Mips Technologies, Inc.

Zenverge, Inc.

Freescale Semiconductor,inc.

Rojit Jacob

Alexander Naum Kipnis

Behzad R Sayyah

A method and system are disclosed for managing cache memory in a dual-pipelined CABAC encoder. A request for a context model is received from both encoder pipelines. If the requested context model is not stored in cache, the requested context model is retrieved from a context table. At least one context model stored in cache is written to the context table. The retrieved context model is updated and written to the cache. If the requested context model is stored in cache, and if the requested context model was updated in the previous clock cycle, the requested context model is retrieved from the pipeline, updated, and written to cache. If the requested context model is not stored in cache, and if the requested contest model was not updated in the previous clock cycle, the requested context model retrieved from cache, updated, and written back to cache.

Context model cache-management in a dual-pipeline CABAC architecture

A method and system are disclosed for the lossless compression of video data in a synchronous pipelined environment. One or more syntax elements of video data are binarized into one or more ordered bins. A first context model associated with a first bin and a second context model associated with a second bin are received. The first bin is encoded based on the first context model and the second bin is encoded based on the second context model, both bins being encoded within the same clock cycle. One or more encoded bits are outputted based on encoding the first and second bin. In one embodiment, the first bin is encoded in a first pipeline and the second bin is encoded in a second pipeline. In this embodiment, two bins may be encoded every clock cycle, one per pipeline. Further, in one embodiment, multiple context models are received and one context model is selected by each pipeline for encoding. After encoding, one or more context models may be updated and stored.

Dual-pipeline CABAC encoder architecture

A system (and a method) are disclosed for intelligently fetch one or multiple reference blocks from memory for each block to be motion compensated or motion estimated within a video processing system. The system includes a reference block configuration evaluation unit and a motion compensation memory fetching unit. The reference block configuration evaluation unit analyzes the reference block configuration of the block being motion compensated with a plurality of reference block configurations of its neighboring blocks. In response to a reference block configuration evaluation result, the reference block configuration evaluation unit decides the configuration of reference blocks to be fetched from a memory. The motion vector memory fetching unit fetches the number of reference blocks for motion compensation accordingly.

Optimized motion compensation and motion estimation for video coding

Resource requests are allocated by storing resource requests in a queue slots in a queue. A token is associated with one of the queue slots. During an arbitration cycle, the queue slot with the token is given the priority to the resource. If the queue slot with the token does not include a request, a different queue slot having the highest static priority and including a request is given access to the resource. The token is advanced to a different queue slot after one or more arbitration cycles. Requests are assigned to the highest priority queue slot, to random or arbitrarily selected queue slots, or based on the source and/or type of the request. One or more queue slots may be received for specific sources or types of requests. Resources include processor access, bus access, cache or system memory interface access, and internal or external interface access.

Efficient resource arbitration

A cache tag comparison unit in a cache controller evaluates tag data and error correction codes to determine if there is a cache hit or miss. The cache tag comparison unit speculatively compares the tag data with the request tag without regard to error correction. The error correction code verifies whether this initial comparison is correct and provides a confirmed cache hit or miss signal. The tag data is compared with the request tag to determine a provisional cache hit or miss, and in parallel, the error correction code is evaluated. If the error code evaluation indicates errors in the tag data, a provisional cache hit is converted into a cache miss if errors are responsible for a false match. If the error code evaluation identifies the locations of errors, a provisional cache miss is converted into a cache hit if the errors are responsible for the mismatch.

Growing community of inventors

Sunnyvale, CA, United States of America

Rojit Jacob