Nxp Usa, Inc.

Freescale Semiconductor,inc.

Roi Menahem Shor

Avraham Horn

Shay Shpritz

Avraham Dov Gal

Peter Zahariev Rashev

Ori Goren

Igor Levakov

Yael Rozin

Haim Bareket

Frederic Fernez

Avi Gal

Igor Levacov

A method including receiving, by a radio equipment control (REC) device of a wireless communication system over an interface link, time domain compressed data from a radio equipment (RE) device at a first data transmission rate. The method further including transforming, by the REC device, the time domain compressed data to frequency domain decompressed full rate data for a second transmission data rate utilizing a Fast Fourier processing engine of the REC device.

Method and system for processing lower NFFT LTE rates over CPRI link

A method performed by a radio equipment control (REC) device, including storing values of link configuration registers of a radio equipment control (REC) device at shadow registers of the REC device in response to determining that a synchronization of a current communication link between the REC device and a radio equipment (RE) device has been lost. The method further including re-establishing the current communication link based on the values of the link configuration registers stored at the shadow registers of the REC device.

System and method for radio base station device hot reconnection (hot plugging)

A method including performing a delay measurement of a first round trip delay value of an interface link, the first round trip delay value based on a transmission of a first REC synchronization signal to a RE and when a REC receives a first RE synchronization signal back, wherein frames transmitted by the REC are synchronized based upon the first REC synchronization signal, and frames transmitted by the RE are synchronized based upon the first RE synchronization signal. Calculating a first delay change value between the first round trip delay value and a previous round trip delay value, in response to determining that the first delay change value violates a delay tolerance value, transmitting an offset indicator that indicates an amount of offset the RE is to shift the first RE synchronization signal at a future time, and transmitting frames from the REC after shifting the first REC synchronization signal.

System and method for automatic delay compensation in a radio base station system

A method performed by a radio base station, the method including determining a link configuration of a first communication link, the first communication link being a current communication link between a first radio equipment control (REC) device and a radio equipment (RE) device. The method further including in response to determining that a second communication link between a second REC device and the RE device is to replace the current communication link, instead of the first communication link, establishing, by the second REC device, the second communication link based on the determined link configuration of the first communication link.

System and method for radio base station device hot switching and hot swapping

A method performed by a radio base station, the method including receiving streaming data information, the data information includes a first portion from a first set of antenna carriers and a second portion from a second set of antenna carriers, wherein the first portion is to be processed prior to the second portion. The method further including streaming the first portion of the data information from a radio equipment control device in a first data frame over an interface link that is configured to operate based on a first mapping configuration that indicates a set of locations of the first data frame at which the first portion of information is to be streamed, and streaming the second portion of the data information from the REC device in a second data frame over the interface link that is configured to operate based on a second mapping configuration.

System and method for on-the-fly modification of the properties on an active antenna carrier in radio base station communication operation

The present application relates to a Common Public Radio Interface, CPRI, lane controller and a method of operating thereof. The CPRI lane controller comprises a transaction counter, a symbol counter and a comparator. The transaction counter is provided for maintaining a current aggregated transactions' size, Size, representative of an accumulated size of DMA transactions performed by a DMA controller in response to symbols transferred on a CPRI link from or to the CPRI lane controller. The symbol counter is provided for maintaining a current aggregated expected symbols' size, Size, representative of an accumulated size of a sequence of transferred symbols and a currently transferred symbol. The comparator is configured to issue a symbol awareness signal, SAS, in case the current aggregated transactions' size, Size, exceeds the current aggregated expected symbols' size, Size.

Common public radio interface, CPRI, lane controller and method of operating thereof

A method performed by a radio base station, the method including determining that one of a Direct Memory Access (DMA) buffers of a communication link for a service provider has gone beyond a DMA buffer limit (empty or full), the communication link between a radio equipment control (REC) device and a radio equipment (RE) device that is operating based on a first bandwidth configuration of the communication link. The method further including in response to determining that the communication link is to change operation (due to reaching the DMA buffer limit) based on a second bandwidth configuration of the communication link, instead of the first bandwidth configuration, continuing operation of the communication link based on the second bandwidth configuration. The method further including that after going back under the DMA buffer limit, the communication link continuing operation based on the original first bandwidth configuration.

System and method for automatic load adaptive antenna carrier bandwidth dynamic reconfiguration in radio base station system

An equalizer includes an equalizer circuit including a signal input to receive a first frequency-domain signal, another signal input to receive a second frequency-domain signal, and an equalized signal output to provide a first equalized signal based upon the first and second frequency-domain signals. Another equalizer circuit includes a signal input to receive a third frequency-domain signal, another signal input to receive a fourth frequency-domain signal, and an equalized signal output to provide a second equalized signal based upon the third and fourth frequency-domain signals. A third equalizer circuit includes a signal input coupled to the equalized signal output of the first equalizer circuit to receive the first equalized signal, another signal input coupled to the equalized signal output of the second equalizer circuit to receive the second equalized signal, and an equalized signal output to provide a third equalized signal based upon the first and second equalized signals.

System and method for large dimension equalization using small dimension equalizers

A predistortion method and apparatus are provided which use a DPD actuator () to apply a memory polynomial formed with first DPD coefficients to a first input signal x[n], thereby generating a first pre-distorted input signal y[n] which is provided to the non-linear electronic device () to produce the output signal, where the memory polynomial may be adaptively modified with a digital predistortion adapter () which computes second DPD coefficients u[n] with an iterative fixed-point conjugate gradient method which uses N received digital samples of the first pre-distorted input signal y[n] and a feedback signal z[n] captured from the output signal to process a set of conjugate gradient parameters (u, b, v, r, &#x3c9;, &#x3b1;, &#x3b2;) at each predetermined interval, thereby updating the first DPD coefficients with the second DPD coefficients u[n] generate a second pre-distorted input signal which is provided to the non-linear electronic device.

Fixed-point conjugate gradient digital pre-distortion (DPD) adaptation

An equalizer circuit of a particular equalization stage of a equalizer circuit is omitted, and input signals that would have otherwise been received at the omitted equalization circuit bypass the equalization stage and are instead processed at an equalizer circuit included at the next stage. Thus, a subset of the received frequency-domain signals can be processed by equalizer circuits at a first stage, while the remaining received frequency-domain signals bypass the first stage and are processed at an equalizer circuit included at a second stage.

System and method for large dimension equalization using small dimension equalizers and bypassed equalizers

A method is described for predistorting an input signal to compensate for non-linearities caused to the input signal in producing an output signal. The method comprises: providing an input for receiving a first input signal as a plurality of signal samples,[n], to be transmitted over a non-linear element; providing at least one digital predistortion block comprising, a plurality of IQ predistorter cells coupled to the input, each comprising a lookup table (LUT) for generating an LUT output. The at least one digital predistortion block block is configured to apply interpolation between LUT entries for the plurality of LUTs; and generate an output signal,[n], by each of the plurality of IQ predistorter cells by adaptively modifying the first input signal using interpolated LUT entries to compensate for distortion effects in the non-linear element. A combiner may be provided configured to combine the output signal samples, y, from the plurality of IQ predistorter cells into a combined signal to generate the output signal,[n], for transmission to the non-linear element. An error calculation block may be coupled to a digital predistortion adaptation block to determine and modify a predistortion performance.

Adaptive high-order nonlinear function approximation using time-domain volterra series to provide flexible high performance digital pre-distortion

A controller device can control the time of a slave sub-system in a chain in a base station system. The controller device comprises a slave transceiver for receiving/transmitting from/to a master sub-system, and a synchronization device for synchronizing a clock of the slave transceiver to a clock of the master sub-system based on the received signal received from the master sub-system. The synchronization circuitry comprises a clock input port for receiving an external clock signal from an external clock generator. At a received signal input port the received signal can be received from the master transceiver. A tracking loop couples the received signal input and the second phase input to a control input of a controllable PLL, for providing a negative feedback which controls a phase and/or frequency of the feedback signal to counter the phase and or frequency error between the external clock signal and the received signal.

Synchronization circuitry, common public radio interface enable device, and a method of synchronizing a synchronized clock signal of a second transceiver to a clock of a first transceiver

A digital front end channelization device for one or more carrier signals comprises a per carrier section and a composite section. The composite section may include signal processing units, each of which may include an inverse Fourier transform unit for transforming a composite carrier signal into a time domain signal, a sample detection and selection unit for detecting and selecting a peak of the time domain signal, a clipping unit for clipping the time domain composite carrier signal to produce an error signal, a Fourier transform unit, for transforming the error signal into a frequency domain error signal, a frequency shaping unit for frequency shaping the frequency domain error signal, a summation unit for subtracting the frequency shaped frequency domain error signal from the composite carrier signal, and a phase selection unit for phase adjustment of the resulting signal.

Digital front-end channelization device

A method and apparatus are used to predistort input signal samples according to Volterra Series Approximation Model using one or more digital predistortion blocks () having a plurality of predistorter cells (-), each including an input multiplication stage (-) for combining absolute sample values received from an absolute sample delay line () into a first stage output, a lookup table () connected to be addressed by the first stage output for generating an LUT output, and a plurality of output multiplication stages (--) for combining the LUT output with samples received from the amplitude sample delay line () and signal sample delay line () to generate an output signal sample yfrom said predistorter cell, where the output signal samples yfrom the predistorter cells are combined at an output adder circuit () to generate one or more Volterra terms of a combined signal (y[n]).

Interfacing between radio units in a base station in a mobile communication system may use synchronized clocks. A controller device has a tracking clock circuit for generating a transmit clock, the tracking clock circuit comprising a clock input for receiving a reference clock and a sync input for receiving an external synchronization signal. A multiplying phase locked loop generates the transmit clock in dependence on the reference clock and a divider output of a controllable divider coupled to the transmit clock. A tracking loop has a phase detector coupled to the sync input and the divider output for detecting a phase error between the external synchronization signal and transmit clock, and a phase control circuit for generating a phase control signal based on the phase error, the phase control signal being coupled to a control input of the controllable divider for adapting the division function.

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Tel Aviv, Israel

Roi Menahem Shor