Mellanox Technologies, Ltd.

Mellanox Technologies Tlv Ltd.

Birad-research & Development Company Ltd.

Roi Levi

Igal Kushnir

Eshel Gordon

Naor Peretz

Joseph Shor

Yoav Weizman

Ayal Eshkoli

Boris Sharav

Technologies for duty cycle distortion (DCD) estimation are described. A transmitter includes a first output driver comprising a first complementary metal-oxide semiconductor (CMOS) amplifier and a first attenuator coupled to an output of the first CMOS amplifier. The first CMOS amplifier receives an input signal and outputs an intermediate signal to the first attenuator. The first attenuator receives the intermediate signal and outputs an output signal having a signal swing that is less than a signal swing of the input signal. A first duty cycle correction (DCC) loop is coupled to the first output driver. The first DCC loop estimates first DCD in the intermediate signal output by the first CMOS amplifier.

Duty cycle distortion (DCD) sampling in a low-swing transmitter

A digital-to-charge converter, a digital-to-analog converter, and a method of operating a digital-to-charge converter are provided. An illustrative method of operating a digital-to-charge converter is provided that includes: receiving a digital input signal at the digital to charge converter, charging one or more capacitors during a pre-evaluation period, where the one or more capacitors are charged with a supply voltage based the digital input signal, disconnecting the one or more capacitors from the supply voltage during an evaluation period, and generating an analog output signal from the digital to charge converter based on an evaluation of charge of the one or more capacitors during the evaluation period.

High speed charge mode digital-to-analog converter

Technologies for jitter extraction are described. A receiver device includes an analog-to-digital converter (ADC) and a signal processing circuit. The signal processing circuit includes an equalizer block to output current data based on samples from the ADC. A clock-recovery (CR) block includes a timing error detector (TED) or a phase detector to measure a sampling offset. The CR block can use the sampling offset to control sampling of subsequent data by the ADC. A jitter extraction block can use the sampling offset to re-sample the current data to obtain re-sampled data based on the sampling offset to remove jitter from the current data.

A digital to analog converter (DAC) includes a first amplifier configured to receive a first bit of a data block as an input and output a first signal based on a value of the first bit of the data block, a first filter circuit configured to filter the first signal, an output configured to output an analog signal based on a combination of the filtered first signal and a second signal that represents a value of a second bit of the data block.

Systems, methods, and devices for digital-to-analog conversion in data transmission

A data modulator for a transmitter includes a multiplexer configured to receive, at a first rate, a first data stream including a plurality of first symbols and a second data stream including a plurality of second symbols. The multiplexer is configured to selectively output, based on a first clock signal, the plurality of first symbols and the plurality of second symbols to form a third data stream that achieves a second rate greater than the first rate for transmission of the third data stream by the transmitter.

Systems, methods, and devices for high-speed data modulation

A physical unclonable function (PUF) array includes a plurality of PUF transistor cells each of which includes at least one inverter. An input and an output of the at least one inverter are shorted to a first reference node. There is adjustment circuitry for adjusting a reference voltage of the first reference node, and measurement circuitry for measuring a trip point of the at least one inverter. If the trip point is close to the reference voltage then bits of the at least one inverter are defined as unstable.

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Bruchin, Israel

Roi Levi