Amazon Technologies, Inc.

Roi Ben Haim

Guy Nakibly

Adi Habusha

Ariel Pescovsky

Erez Izenberg

Yaniv Shapira

Itai Avron

Uri Leder

Sergey Kleyman

Simaan Bahouth

Muhamad Grefat

An integrated circuit to synchronize a pulse signal from a first clock domain to a second clock domain includes a first flip-flop and a second flip-flop. The first flip-flop has a first stage input, a first clock input, and a first stage output. The first clock input is driven by a first clock signal of the first clock domain, and the first stage input is driven by a result of XOR-ing the input pulse signal and the first stage output. The second flip-flop has a second stage input, a second clock input, and a second stage output. The second clock input is driven by a second clock signal of the second clock domain, and the second stage input is driven by the first stage output. The synchronized output pulse signal is generated by XOR-ing the second stage output with the first stage output.

Low latency synchronization

A link layer reliability (LLR) circuit of a communication device can receive an indication that a link down event has occurred on a bus link with a peer device. The LLR circuit can prevent the link down event from triggering a reset of configuration registers containing bus settings for the bus link. Once the bus link has been restored, the LLR circuit can send a retry request to the peer device indicating an expected sequence number associated with a transaction that the LLR circuit is expecting from the peer device. The LLR circuit may receive a retry acknowledgment from the peer device indicating receipt of the retry request for the transaction corresponding to the expected sequence number, and payload data for the transaction corresponding to the expected sequence number.

Link down resilience

Systems and methods are provided to differentiate different types of traffic going through the same physical channel such that the traffic flow for different traffic types does not impact each other. The physical channel can be configured to support a plurality of virtual channels. Each transaction that needs to be communicated through the physical channel can be classified into a certain traffic type, and each traffic type can be assigned to a virtual channel. Each transaction can be communicated on a respective virtual channel based on the corresponding traffic type. If the traffic flow through a first virtual channel for a transaction slows down, the traffic flow through a second virtual channel for another transaction can continue without getting impacted by the slow down on the first virtual channel.

Traffic separation in a multi-chip system

Ordering rules, such as those enforced by the peripheral component interconnect express (PCIe) protocol for data communications, can be intelligently enforced for independent transactions. A single device might host or be associated with multiple PCIe devices, such as virtual machines, and treating requests from these separate PCIe devices as coming from separate domains enables the ordering rules to be bypassed for certain transactions. Further, since a virtual machine might host multiple applications or be associated with multiple processors that can submit independent requests, the ordering rules can be bypassed at the transaction level in at least some instances. The ability to intelligently bypass ordering rules can help to improve the performance of the overall system, as requests do not need to be unnecessarily delayed and data storage capacity can be more fully utilized.

Transaction ordering management

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Netanya, Israel

Roi Ben Haim