Western Digital Technologies, Inc.

Sandisk Technologies Inc.

Other

Micron Technology Incorporated

Rohit Sehgal

Sahil Sharma

Niles Yang

Phil Reusswig

Nian Niles Yang

Philip David Reusswig

Abhilash Ravi Kashyap

Zachary David Shepard

Eran Sharon

Alexander Bazarsky

Dudy David Avraham

Mohan Dunga

Daniel Joseph Linnen

Aaron Lee

Karin Inbar

Grishma Shah

Sarath Chandran Puthenthermadam

Dongxiang Liao

Pitamber Shukla

Ashish Ghai

Avinash Rajagiri

Srikar Peesari

Mahim Raj Gupta

Gautham Reddy

Piyush Anil Dhotre

Mohsen Purahmad

Piyush Dhotre

Rohan Dhekane

Vishal Tanna

Weijie Yu

Abhi Kashyap

Gilad Koren

Eishan Mirakhur

A system can include a first memory device including a persistent byte-addressable memory; a second memory device; and a processing device, operatively coupled with the first and second memory devices, to perform operations including: receiving a first host command to write or read user data; storing the user data in the persistent byte-addressable memory with a first data granularity; and transmitting the user data stored in the persistent byte-addressable memory to the second memory device. The operations can further include: responsive to determining that a power loss event has occurred during an operation to a particular data packet in a size of the first data granularity in the persistent byte-addressable memory, determining whether the first host command associated with the particular data packet is completely executed; and responsive to determining that the first host command is not completely executed, restoring the particular data packet in the persistent byte-addressable memory.

Using a persistent byte-addressable memory in a compute express link (CXL) memory device for efficient power loss recovery

Data storage devices, such as solid state drives (SSDs), are disclosed. A read threshold calibration operation is utilized to generate a calibrated read threshold for one or more voltage states of a cell of a MLC memory. A single-level cell (SLC) read is then executed to sense the ratio of bit values at the read thresholds of the voltage states, where SLC read refers to reading at a single read threshold, rather than to the cell type. The sensing results in a binary page with certain statistics of 1's and 0's. The ratio of 1's (or 0's) in the binary page is used to determine a deviation from the expected ratio, where the deviation is used to adjust the calibrated read threshold to match the voltage states of the MLC memory.

Detection of page discrepancy during read threshold calibration

A data storage system includes a storage medium and a storage controller configured to perform interface training operations. The interface training operations include loading a test data pattern into a first controller buffer of the storage controller, loading the test data pattern into a first storage medium buffer of the storage medium, setting a first read voltage or timing parameter at the storage controller, transferring the test data pattern from the first storage medium buffer to a second controller buffer of the storage controller using the first read voltage or timing parameter, comparing the test data pattern in the first controller buffer with the test data pattern in the second controller buffer, and determining a first read transfer error rate based on the first comparison.

Storage medium-assisted system interface training scheme

Methods and apparatus for storing parity bits in an available over provisioning (OP) space to recover data lost from an entire memory block. For example, a data storage device may receive data from a host device, write the data to a block, and generate a corresponding block parity. The device may then determine a bit error rate (BER) of the block and an average programming duration to write the data written to the block, calculate a probability of the block becoming defective based on the BER and the average programming duration, and comparing the probability of the block to a set of probabilities respectively corresponding to a set of worst-performing blocks in a NVM. Thereafter, the device may write the block parity to an available over provisioning (OP) space in the NVM responsive to the probability of the block being greater than any probability in the set of probabilities.

Using over provisioning space for selectively storing block parity

A storage system and method for boundary wordline data retention handling are provided. In one embodiment, the storage system includes a memory having a single-level cell (SLC) block and a multi-level cell (MLC) block. The system determines if the boundary wordline in the MLC block has a data retention problem (e.g., by determining how long it has been since the boundary wordline was programmed). To address the data retention problem, the storage system can copy data from a wordline in the SLC block that corresponds to the boundary wordline in the MLC block to a wordline in another SLC block prior to de-committing the data in the SLC block. Alternatively, the storage system can reprogram the data in the boundary wordline using a double fine programing technique.

Storage system and method for boundary wordline data retention handling

Systems and methods for storage systems using storage device monitoring for load balancing are described. Storage devices may be configured for data access through a common data stream, such as the storage devices in a storage node or server. Data operations from the common data stream may be distributed among the storage devices using a load balancing algorithm. Performance parameter values, such as grown bad blocks, program-erase cycles, and temperature, may be received for the storage devices and used to determine variance values for each storage device. Variance values demonstrating degrading storage devices may be used to reduce the load allocation of data operations to the degrading storage devices.

Storage device parameter monitoring for load balancing

A storage system comprises a controller connected to blocks of non-volatile memory cells. The memory cells can be operated as single level cell ('SLC') memory cells or multi-level cell ('MLC') memory cells. To increase write performance for a subset of memory cells being operated as SLC memory cells, the controller performs a deeper erase process and a weaker program process for the subset of memory cells. The weaker program process results in a programmed threshold voltage distribution that is lower than the &#x201c;nominal&#x201d; programmed threshold voltage distribution. Having a lower programmed threshold voltage distribution reduces the magnitude of the programming and sensing voltages needed and, therefore, shortens the time required to generate the programming and sensing voltages, and reduces power consumption.

Non-volatile storage system with fast SLC operation

A method of operating a storage device, including; performing, by a non-volatile memory, an erase operation on a block of memory in the non-volatile memory, where the non-volatile memory is coupled to a controller; receiving, by the non-volatile memory, a host-transaction within a first time period, where, the non-volatile memory is coupled to a host device; and suspending, by the non-volatile memory, an erase operation in response to receiving the host-transaction by: determining the erase operation has completed a charge phase; and suspending the erase operation during a pulse phase of the erase operation. The method additionally includes the non-volatile memory maintaining a loop counter and a pulse counter, where: the loop counter increments in response to completion of an erase loop, and the pulse counter increments in response to completion of an erase pulse, where the erase pulse is applied during a pulse phase of the erase operation.

Erase suspend scheme in a storage device

Preparing a key block in a memory system. Various methods include: selecting a candidate key block of memory; checking a quality of the candidate key block using a word line of the candidate key block; altering operating parameters of the candidate key memory block; and registering the candidate key memory block as the key block. Where altering the operating parameters includes replacing a first set of parameters associated with the first memory block with a second set of parameters, where the first set of parameters includes a first erase parameter, a first program parameter, and a first read parameter, where the memory block operating in a normal block mode is accessed using the first set of parameters, and the second set of parameters includes a second erase parameter, a second program parameter, and a second read parameter, where the first memory block is accessed using the second set of parameters.

Method of identifying and preparing a key block in a flash memory system and memory controller therefor

A data storage system performs operations including determining an endurance level of a block of memory cells; adjusting a read performance profile for the block of memory cells based on the determined endurance level; receiving a data read command specifying data to be read from a particular memory cell of the block of memory cells; and in response to the data read command, performing a read operation on the particular memory cell using the adjusted read performance profile.

Adaptive read trim for second read data retention

Techniques are described for performing a read scan process on a non-volatile memory system in order to determine memory blocks that may have a high bit error rate, where if such blocks are found they can be refreshed. Rather than work through the blocks of a memory system sequentially based on the physical block addresses, the memory system maintains a measure of data quality, such as an estimated or average bit error rate, for multi-block groups. For example, the groups can correspond to regions of memory die in the system. The groups are ranked by their data quality, with the groups being scanned in order of the data quality. The blocks within a group can also be ranked, based on factors such as the program/erase count.

Enhancing the effectiveness of read scan performance and reliability for non-volatile memory

A Data Storage Device (DSD) or a server is set to an unlocked state to allow access to a memory of the DSD or to a DSD of the server. Communication is established with an access station using a wireless communication interface, and an access code is received from the access station via the wireless communication interface. If the received access code is determined to be valid, the DSD or server is set to the unlocked state. According to another aspect, communication is established with a DSD or a server using a wireless communication interface, and an access code is generated and sent to the DSD or the server for setting the DSD or the server to the unlocked state.

Location-based authentication and monitoring for data storage devices

In one embodiment, there is a method for implementing balancing block wearing leveling at a storage device including one or more single level cell (SLC) blocks in a SLC block pool and one or more non-single level cell (nSLC) blocks in a nSLC block pool for storing data and a memory controller for performing operations on the SLC blocks and nSLC blocks, the method comprising: at the memory controller: receiving a first request to perform a wear leveling operation on a respective block pool of one of: the SLC block pool and the nSLC block pool; determining whether one or more blocks in the respective block pool meet block pool transfer criteria; in response to a determination that the one or more blocks in the respective block pool meets block pool transfer criteria, reclassifying the one or more blocks in the respective block pool as the other of the SLC block pool and the nSLC block pool; and in response to a determination that the one or more blocks in the respective block pool does not meet block pool transfer criteria, refraining from reclassifying the one or more blocks in the respective block pool as the other of the SLC block pool and the nSLC block pool.

Balancing the block wearing leveling for optimum SSD endurance

Detecting a faulty memory block. Various methods include: performing a read operation on a memory block of the memory array, the read operation generates a failed bit count; determining the failed bit count in above a value associated with an overall failed bit count; determining the failed bit count is above a threshold value; in response, performing a confirmation process on the memory block, the confirmation process defining a number of consecutive erase cycles and a level of an erase cycle, the confirmation process results in erase pass or erase fail; and marking the memory block for garbage collection in response to determining the confirmation process results in erase fail. Methods additionally include setting the level of the erase cycle by modifying at least one selected form the group comprising: an erase voltage parameter; an erase verify parameter; and a number of bits ignored during the erase cycle.

Detecting a faulty memory block

The present disclosure, in various embodiments, describes technologies and techniques for use by a memory controller or similar device for storing sequential image data or other data streams composed of pages of data. In one example, the memory controller compares data within current and previous image frames on a page-by-page basis. If a pair of pages match, the memory controller creates a link between the two pages so the duplicate page need not be stored. During a subsequent read operation, the flash controller accesses stored links to identify the physical storage addresses of any matching pages stored in connection with a previous frame to permit efficient retrieval. In some examples, a page is compared with both the previous corresponding page and with the neighboring pages of that previous page. Exemplary read, write and erase operations are described herein using the links.

Growing community of inventors

San Jose, CA, United States of America

Rohit Sehgal