Apple Inc.

Intel Corporation

Samsung Electronics Co., Ltd.

Rohit Natarajan

Rohit Kumar Gupta

Sridhar Lakshmanamurthy

Chen-Chi Kuo

Prashant R Chandra

Harshavardhan Kaushikkar

Jurgen M Schulz

Srinivasa Rangan Sridharan

Mark B Rosenbluth

Connie W Cheung

Christopher D Shuler

Jeonghee Shin

Thomas T Zou

James D Guilford

Paolo Sacchetto

Mahesh B Chappalli

Christopher P Tann

Marc Joseph DeVincentis

Gregory S Mathews

Sanjay Mani

Vanessa Cristina Heppolette

Varaprasad V Lingutla

Muditha Kanchana

Wolfgang H Klingauf

Salman Latif

Kin-Yip Liu

Meir Harar

Anjana Subramanian

Yu Simon Zhang

Mukul A Joshi

Si Mohamed Aziz Sbai

Timothy M Henigan

A memory controller may include a dynamic arbitration scheme to dynamically vary arbitration factors of two or more traffic classes based on dynamic latency tolerance, requested and available bandwidths on an interconnect from source agents to memory controllers, and other dynamic and static factors.

Bandwidth-aware fabric traffic shaping

A non-transitory computer-readable medium is disclosed, the medium having instructions stored thereon that are executable by a computer system to perform operations that may include allocating a plurality of storage locations in a system memory of the computer system to a buffer. The operations may further include selecting a particular order for allocating the plurality of storage locations into a cache memory circuit. This particular order may increase a uniformity of cache miss rates in comparison to a linear order. The operations may also include caching subsets of the plurality of storage locations of the buffer using the particular order.

Allocation of a buffer located in system memory into a cache memory

Systems, methods, and devices are described that may mitigate pixel and touch crosstalk noise. A touch processing system may compensate touch scan data to reduce the noise based on a luminance value. An image processing system may determine the luminance value based on image data and a display brightness value of an electronic display. Using the compensated touch scan data, the touch processing system may determine a proximity of a capacitive object to at least one touch sense region of the electronic display.

Pixel array and touch array crosstalk mitigation systems and methods

An electronic device may include an electronic display to display an image based on processed image data. The electronic device may also include image processing circuitry to generate the processed image data based on input image data and previously determined data stored in memory. The image processing circuitry may also operate according to real-time computing constraints. Cache memory may store the previously determined data in a provisioned section of the cache memory allotted to the image processing circuitry. Additionally, a controller may manage reading and writing of the previously determined data to the provisioned section of the cache memory.

Guaranteed real-time cache carveout for displayed image processing systems and methods

Techniques are disclosed relating to merging virtual communication channels in a portion of a computing system. In some embodiments, a communication fabric routes first and second classes of traffic with different quality-of-service parameters, using a first virtual channel for the first class and a second virtual channel for the second class. In some embodiments, a memory controller communicates, via the fabric, using a merged virtual channel configured to handle traffic from both the first virtual channel and the second virtual channel. In some embodiments, the system limits the rate at which an agent is allowed to transmit requests of the second class of traffic, but requests by the agent for the first class of traffic are not rate limited. Disclosed techniques may improve independence of virtual channels, relative to sharing the same channel in an entire system, without unduly increasing complexity.

Communication channels with both shared and independent resources

A configurable interface circuit is disclosed. An integrated circuit (IC) having a particular configuration. The IC includes a memory system and a communication fabric coupled to the memory system. The IC further includes a plurality of agent circuits configured to make requests to the memory system that are in a first format that is not specific to the particular configuration of the IC. A plurality of interface circuits is coupled between corresponding ones of the plurality of agent circuits and the communication fabric. A given one of the plurality of interface circuits is configured to receive a request to the memory system in the first format and output the request in a second format that is specific to the particular configuration of the IC.

Configurable interface circuit

An apparatus includes a cache controller circuit and a cache memory circuit that further includes cache memory having a plurality of cache lines. The cache controller circuit may be configured to receive a request to reallocate a portion of the cache memory circuit that is currently in use. This request may identify an address region corresponding to one or more of the cache lines. The cache controller circuit may be further configured, in response to the request, to convert the one or more cache lines to directly-addressable, random-access memory (RAM) by excluding the one or more cache lines from cache operations.

Dynamic allocation of cache memory as RAM

Systems, apparatuses, and methods for dynamically partitioning a memory cache among a plurality of agents are described. A system includes a plurality of agents, a communication fabric, a memory cache, and a lower-level memory. The partitioning of the memory cache for the active data streams of the agents is dynamically adjusted to reduce memory bandwidth and increase power savings across a wide range of applications. A memory cache driver monitors activations and characteristics of the data streams of the system. When a change is detected, the memory cache driver dynamically updates the memory cache allocation policy and quotas for the agents. The quotas specify how much of the memory cache each agent is allowed to use. The updates are communicated to the memory cache controller to enforce the new policy and enforce the new quotas for the various agents accessing the memory.

Application aware SoC memory cache partitioning

A system and corresponding method captures speculative and concurrent trace-data and trace-clock information from core processing units of a System on a Chip (SOC). An interface receives trace data from at least one core processing unit, and a storage array stores the trace data in two different modes of operation. In the first mode, which occurs prior to a predetermined operating state of the SOC, the storage array operates in a circular buffer mode in which the newest trace data overwrites the oldest trace data when the storage array becomes full In the second mode, which occurs after the predetermined operating state of the SOC, the storage array operates in a FIFO mode in which the newest trace data is written into the storage array and the oldest trace data contained in the storage array is output to a debug processing core unit of the SOC.

Low-overhead debug architecture using a speculative, concurrent and distributed data capture and propagation scheme

We describe a system and method to merge and align data from distributed memory controllers. A memory system includes a command bus to transmit a predetermined memory access command, and a memory interface to manipulate data from at least two memory channels, each memory channel corresponding to a portion of a distributed memory, responsive to the predetermined memory access command. The memory interface includes a plurality of memory controllers coupled to the command bus, each memory controller being operable to control a corresponding memory channel responsive to the predetermined memory access command, and a push arbiter coupled to each memory controller. The push arbiter being is operable to merge and align data retrieved responsive to each split read align command.

Apparatus and method to merge and align data from distributed memory controllers

Methods, software and systems to determine channel ownership and physical block location within the channel in non-uniformly distributed DRAM configurations and also to detect in-range memory address matches are presented. A first method, which may also be implemented in software and/or hardware, allocates memory non-uniformly between a number of memory channels, determines a selected memory channel from the memory channels for a program address, and maps the program address to a physical address within the selected memory channel. A second method, which may also be implemented in software and/or hardware, designates a range of memory to perform address matching, monitors memory accesses and when a memory access occurs with the specified range, perform a particular function.

Method and apparatus utilizing non-uniformly distributed DRAM configurations and to detect in-range memory address matches

A memory controller that includes an interface to a first memory and an interface to a bus coupling the memory controller to at least one processor. The controller also includes circuitry, responsive to read and write commands received over the bus from the at least one processor, to shift data by an amount identified by at least some of the read and write commands.

Memory controller for padding and stripping data in response to read and write commands

In general, in one aspect, the disclosure describes a method of assembling a packet in memory. The method includes reading data included in a first segment of a packet divided into multiple segments and issuing a command to a memory controller that causes the memory controller to shift and write a subset of the read data to a memory coupled to the memory controller. The method also includes saving the remainder of the read data as a first residue, retrieving data included in a second segment of the packet, and writing at least a portion of the retrieved data and the first residue to the memory.

Growing community of inventors

Sunnyvale, CA, United States of America

Rohit Natarajan