Texas Instruments Corporation

Rohit L Bhuva

James L Conner

Michael J Overlaur

Bao G Tran

Tracy S Paulsen

William R Townson

Allen Y Chen

Michael J Overlauer

Robert A Helmick

Walter C Bonneau, Jr

Robert L Gruebel

Mike Overlaur

A method of testing a large integrated circuit (10) of modular design. Test equipment is connected to a dedicated testing pad section (20) for each circuit section (22, 24, 34) of each module (12, 14, 16). The circuit section under test is tested via the testing pad adjacent that circuit section. The test equipment is then stepped to the testing section for the next circuit section. When testing is completed, the testing section is then electrically isolated from the circuit sections to prevent interference with operation of the entire circuit (10).

Large integrated circuit with modulator probe structures

The spatial light modulator (30) of the DMD type having associated memory cells (10) with a single bit line memory read back architecture (54). The memory cells (10) include a charge equalization switch (50) comprising a transistor connected across the bit lines (16,18) of the memory cell (10). This charge equalization transistor (50) is momentarily turned on (T.sub.3) to balance residual charge on the memory cell bit lines (16,18), after a write cycle (T.sub.2) but before the read cycle (T.sub.4). When the memory cell contents are subsequently read (T.sub.4), the memory cell contents will not change state. A single amplifier (54) is connected to one bit line for reading the memory cell contents. The single bit line (18) memory read back architecture provides a more efficient circuit layout to the spacing constraints required with DMDs, consumes less power than designs with a differential amplifier, and additionally, provides yield improvements.

Memory cell with single bit line read back

A digital micro-mirror device (20) for imaging applications, having an array (21) of mirror elements for forming the image, and having data loading circuitry (22, 23) for loading data for addressing the mirror elements. The data loading circuitry (22, 23) has a row of shift registers (23), which receive data and pass the data to latches (22). Each output of the shift registers (23) is connected to a number of latches (22). For loading a row of data, the row is divided into portions, and the shift registers (23) receive the row of data in sequential portions. It delivers each portion to a different set of latches, each set comprised of a latch from each shift register output. Each set of latches holds its portion of the row of data on bit-lines while the remaining portions of the row are input to the shift registers (23) and passed to other sets of latches (22).

Data loading circuit for digital micro-mirror device

A monolithic DMD spatial light modulator (20) including a storage cell array (24) of charge storage elements (30). Each charge storage cell (30) is formed using robust MOS processes, and comprises a pair of capacitors (32) having a polysilicon electrode fabricated over a substrate, and separated by a thin oxide dielectric. Each capacitor (32) is shielded by several light impermeable metal shields (37, 64, 66, 68, 72, 74, 80, 82, 88) to prevent discharging due to light incident to SLM (20). The substrate electrode (38) is encompassed by an n+ doped region (42) providing a source of minority carriers to an inversion region under the polysilicon electrode (50).

Spatial light modulator with buried passive charge storage cell array

A large integrated circuit (10) of modular design, each module (12,14,16) having a circuit section (22,24,34) and a separate dedicated testing pad section (20). Each circuit module (12,14,16) can be individually functionally tested as an independent circuit with conventional prober equipment for defects. Each testing pad section (20) facilitates controlling the entire integrated circuit (10) so that the respective module circuit section (12,14,16) can be tested. Control circuitry (26) comprised of pass gates is provided to isolate the testing pad sections (20) from the operational portion (22,24,34) of the integrated circuit (10) when not under test. The present invention is ideally suited for large spatial light modulators, memory devices and other large sophisticated integrated circuits.

Large integrated circuit with modular probe structures

A digital micro-mirror device (20) for imaging applications, having an array (21) of mirror elements for forming the image and data loading circuitry (22, 23, 24) for loading data for addressing the mirror elements. The data loading circuitry (22, 23, 24) has a row of shift registers (24), which receive one row of data at a time, which they deliver to latches (23). The latches (23) hold the data on bit-lines, which run down columns of the array (21). The row to be loaded is selected with a row decoder (25). A block load circuit (22), comprised of a shift register (35) and logic gates (33) divides each row of memory cells into blocks (31) and ensures that each block of a row of memory cells is sequentially loaded.

Digital micro-mirror device with block data loading

A Spatial Light Modulator (10) having control circuitry (40,42,44,46) which insures that shorts (70,72) between some of the circuitry will result in 'off' state defects. Sets of pixel elements (11) share a memory cell (12), each pixel element (11) in a set being switched to an on or off state by a reset line (13) that is separate from that of the other pixel elements (11) in that set. A pair of address electrode etches (44,46) are separated from each other and straddle a pair of data carrying etches (40,42). A zero is loaded to the data etches (40,42) when not loading memory cell (12) such that a short between the address electrode etches and the data etches will result in an 'off' state pixel defect upon a reset pulse.

Spatial light modulator with reduced possibility of an on state defect

A programmable memory includes a voltage regulator (32) which is disposed between the supply voltage and the matrix supply line (10) for programmable memory cells. Each of the memory cells is comprised of a transistor (12) and a series of fusible link (16). By maintaining a constant voltage on the matrix supply line (10), transients on the supply pin of a memory chip cannot cause spurious changes in the logic state of the memory cell resulting from parasitic capacitance (28).

On chip voltage regulator for common collection matrix programmable

A circuit (90) converts a true ECL signal to a true TTL signal. The circuit includes a differential circuit (180) that receives an ECL signal having high and low values. The differential circuit produces a differential signal therefrom that has a high value in response to one of the high and low values of the true ECL signal, and a low value in response to the other of the high and low values of the true ECL signal. A first translator circuit (36, 64) has an input (32) coupled to the differential circuit (180). The first translator circuit (36, 64) transmits a true low TTL output (56) signal having a voltage level referenced to the voltage level of a TTL low supply voltage in response to receiving a high value of the differential signal. A second translator circuit (46, 52) has an input (38) and is coupled to a TTL high supply voltage and the output (56). An input signal appearing on the input (38) of the second translator circuit has a voltage level related to the voltage level of the differential signal (32). The second translator circuit (46, 52) transmits a high TTL output signal having a voltage level referenced to the voltage level of the TTL high supply voltage in response to the differential signal (32) being at a low value.

ECL/TTL conversion circuit and translation programmable array logic

A programmable memory includes a voltage regulator (32) which is disposed between the supply voltage and the matrix supply line (10) for programmable memory cells. Each of the memory cells is comprised of a transistor (12) and a series fusible link (16). By maintaining a constant voltage on the matrix supply line (10), transients on the supply pin of a memory chip cannot cause spurious changes in the logic state of the memory cell resulting from parasitic capacitance (28).

On chip voltage regulator for common collector matrix programmable

A programmable memory includes a memory matrix (34) with a row decode circuit (36) and a column decode circuit (48) operable in the program mode to select one of the memory elements in the memory matrix (34). A current boost circuit (50) is operable to provide increased current to the selected cell such that selection of the cell opens the fuse associated therewith to change the logic state. The pins associated with the column and row addresses have multiple mode functions such that in the normal operating mode they can be assigned other tasks and in the programming mode are utilized primarily for addressing of the memory cells.

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Plano, TX, United States of America

Rohit L Bhuva