Apple Inc.

Nvidia Corporation

Rohit Kumar Gupta

Rohit Natarajan

Ramana V Rachakonda

Peter F Holland

Brad W Simeral

Jurgen M Schulz

Meir Harar

Ziyad Sami Hakura

Manu Gulati

Emmett Michael Kilgariff

Michael C Shebanow

Harshavardhan Kaushikkar

Srinivasa Rangan Sridharan

John H Kelm

Assaf Menachem

Ido Y Soffair

Oren Kerem

Liang Deng

Bruce H Lam

Connie W Cheung

Christopher D Shuler

Douglas E Solomon

Prabhu Rajamani

Thomas T Zou

Paolo Sacchetto

Joseph P Bratt

Mahesh B Chappalli

Ronald P Hall

Christopher P Tann

Kyungtae Han

Marc Joseph DeVincentis

Gurjeet S Saund

Gregory S Mathews

Bernard Joseph Semeria

Roy Gideon Moss

Philip Browning Johnson

Deniz Balkan

Brett Stanley Feero

Richard F Russo

Andrew R Bell

Gaurav Garg

James Vash

Sanjay Mani

James C Bowman

Johnny S Rhoades

Jeff Gonion

Vanessa Cristina Heppolette

Muditha Kanchana

Varaprasad V Lingutla

Deepak Limaye

Wolfgang H Klingauf

Kevin C Wong

Akila C Ganlath

Paul Li

Salman Latif

Saman Naderiparizi

Sayyed Karen Khatamifard

Brett D George

Peter A Lisherness

Jeonghee Shin

Michael D Snyder

Nejib Ammar

Husam Khashiboun

Satoshi Nagashima

Ziran Wang

Si Mohamed Aziz Sbai

Timothy M Henigan

Do Kyung Kim

Paul W Glendenning

Alon Yaakov

Jeffrey D Marker

Chenfan Sun

Techniques are disclosed relating to performing remote invalidation of memory access permission information. In some embodiments, primary processor circuitry is configured to, based on execution of a remote permission table invalidate instruction (e.g., an ISA-defined instruction), send a remote invalidate command to secondary processor circuitry. The secondary processor circuitry includes secondary processor permission circuitry and is configured to, in response to the remote invalidate command sent by the primary processor, invalidate one or more entries in the secondary processor permission circuitry. In some embodiments, the secondary processor performs the invalidate without executing any instructions on the secondary processor circuitry.

Invalidation of permission information stored by another processor

Embodiments relate to streaming convolution operations in a neural processor circuit that includes a neural engine circuit and a neural task manager. The neural task manager obtains multiple task descriptors and multiple subtask descriptors. Each task descriptor identifies a respective set of the convolution operations of a respective layer of a set of layers. Each subtask descriptor identifies a corresponding task descriptor and a subset of the convolution operations on a portion of a layer of the set of layers identified by the corresponding task descriptor. The neural processor circuit configures the neural engine circuit for execution of the subset of the convolution operations using the corresponding task descriptor. The neural engine circuit performs the subset of the convolution operations to generate output data that correspond to input data of another subset of the convolution operations identified by another subtask descriptor from the list of subtask descriptors.

Subtask storage for streaming convolutions in neural network processor

An electronic device may include a display panel. When content of an image frame is expected to consume relatively higher amounts of power, a controller of the electronic device may operate a switch to change a power supply of the display panel to be a power management integrated circuit of the electronic device. However, when content of an image frame is expected to consume relatively less amounts of power, the controller may operate the switch to change the power supply of the display panel to be a power supply of an electronic display, such as a power supply used to power driver circuitry of the electronic display.

Electronic display pipeline power management systems and methods

The disclosure includes embodiments for a medic system to respond to a medical condition of a vehicle occupant. A method according to some embodiments is executed by a processor. The method also includes determining, by the processor, that a driver of an ego vehicle is experiencing a debilitating medical condition. The method also includes overriding a protocol to decrease an autonomy level of the ego vehicle responsive to inattentiveness of the driver to a driving interface of the ego vehicle so that the driver can be inattentive to the driving interface and the autonomy level is not decreased. The method also includes modifying an operation of an autonomous driving system of the ego vehicle to increase the autonomy level of the ego vehicle to decrease a driving responsibility of the driver responsive to the debilitating medical condition.

Medical emergency detection in-vehicle caretaker

In an embodiment, a system may include one or more processors forming central processing units (CPUs) in the system, a display controller configured to display frames on a display device, a memory controller configured to control a memory, and a power management circuit. The power management circuit may be configured to establish one of a plurality of power states in the system. In a first power state, the display controller and the memory controller are powered on while the CPUs are powered off. The display controller may be configured to read a plurality of prerendered frames from the memory and display the plurality of prerendered frames at times specified for each of the plurality of prerendered frames.

System on a chip that drives display when CPUs are powered down

A non-transitory computer-readable medium is disclosed, the medium having instructions stored thereon that are executable by a computer system to perform operations that may include allocating a plurality of storage locations in a system memory of the computer system to a buffer. The operations may further include selecting a particular order for allocating the plurality of storage locations into a cache memory circuit. This particular order may increase a uniformity of cache miss rates in comparison to a linear order. The operations may also include caching subsets of the plurality of storage locations of the buffer using the particular order.

Allocation of a buffer located in system memory into a cache memory

Systems, methods, and devices are described that may mitigate pixel and touch crosstalk noise. A touch processing system may compensate touch scan data to reduce the noise based on a luminance value. An image processing system may determine the luminance value based on image data and a display brightness value of an electronic display. Using the compensated touch scan data, the touch processing system may determine a proximity of a capacitive object to at least one touch sense region of the electronic display.

Pixel array and touch array crosstalk mitigation systems and methods

An embodiment of an apparatus includes a processing circuit and a system memory. The processing circuit may store a pending request in a buffer, the pending request corresponding to a transaction that includes a write request to the system memory. The processing circuit may also allocate an entry in a write table corresponding the transaction. After sending the transaction to the system memory to be processed, the pending request in the buffer may be removed in response to the allocation of the write entry.

Virtual channel support using write table

Techniques for improving the handling of peripherals in a computer system, including through the use of a DMA control circuit that helps manage the flow of data between memory and the peripherals via an intermediate storage buffer. The DMA control circuit is configured to control timing of DMA transfers between sample buffers in the memory and the intermediate storage buffer. The DMA control circuit may output a priority value of the DMA control circuit for accesses to memory, where the priority value based on stored quality of service (QoS) information and current channel data buffer levels for different DMA channels. The DMA control circuit may separately arbitrate between multiple active transmit and receive channels. Still further, the DMA control circuit may store, for a given data transfer over a particular DMA channel, timestamp information indicative of completion of the DMA and peripheral-side operations.

DMA control circuit with quality of service indications

An electronic device may include an electronic display to display an image based on processed image data. The electronic device may also include image processing circuitry to generate the processed image data based on input image data and previously determined data stored in memory. The image processing circuitry may also operate according to real-time computing constraints. Cache memory may store the previously determined data in a provisioned section of the cache memory allotted to the image processing circuitry. Additionally, a controller may manage reading and writing of the previously determined data to the provisioned section of the cache memory.

Guaranteed real-time cache carveout for displayed image processing systems and methods

Throttling circuitry may throttle the backlight reconstruction via backlight reconstruction and compensation circuitry in a display pipeline when power may be limited. This throttling of the display pipeline may limit a number of cycles that may be used for performing backlight reconstruction and compensation.

Backlight reconstruction and compensation-based throttling

Techniques are disclosed relating to merging virtual communication channels in a portion of a computing system. In some embodiments, a communication fabric routes first and second classes of traffic with different quality-of-service parameters, using a first virtual channel for the first class and a second virtual channel for the second class. In some embodiments, a memory controller communicates, via the fabric, using a merged virtual channel configured to handle traffic from both the first virtual channel and the second virtual channel. In some embodiments, the system limits the rate at which an agent is allowed to transmit requests of the second class of traffic, but requests by the agent for the first class of traffic are not rate limited. Disclosed techniques may improve independence of virtual channels, relative to sharing the same channel in an entire system, without unduly increasing complexity.

Communication channels with both shared and independent resources

A configurable interface circuit is disclosed. An integrated circuit (IC) having a particular configuration. The IC includes a memory system and a communication fabric coupled to the memory system. The IC further includes a plurality of agent circuits configured to make requests to the memory system that are in a first format that is not specific to the particular configuration of the IC. A plurality of interface circuits is coupled between corresponding ones of the plurality of agent circuits and the communication fabric. A given one of the plurality of interface circuits is configured to receive a request to the memory system in the first format and output the request in a second format that is specific to the particular configuration of the IC.

Configurable interface circuit

An apparatus includes a cache controller circuit and a cache memory circuit that further includes cache memory having a plurality of cache lines. The cache controller circuit may be configured to receive a request to reallocate a portion of the cache memory circuit that is currently in use. This request may identify an address region corresponding to one or more of the cache lines. The cache controller circuit may be further configured, in response to the request, to convert the one or more cache lines to directly-addressable, random-access memory (RAM) by excluding the one or more cache lines from cache operations.

Dynamic allocation of cache memory as RAM

Growing community of inventors

Santa Clara, CA, United States of America

Rohit Kumar Gupta