Micron Technology Incorporated

University of Massachusetts

Lodestar Licensing Group LLC

Rohit Kothari

Adam L Olson

John David Hopkins

David A Kewley

Jason Reece

Jason C McFarland

Jeslin J Wu

Lifang Xu

Jian Li

James J Watkins

Harsh Narendrakumar Jain

Xiaosong Zhang

A method of forming a semiconductor device comprising forming a patterned resist over a stack comprising at least one material and removing a portion of the stack exposed through the patterned resist to form a stack opening. A portion of the patterned resist is laterally removed to form a trimmed resist and an additional portion of the stack exposed through the trimmed resist is removed to form steps in sidewalls of the stack. A dielectric material is formed between the sidewalls of the stack to substantially completely fill the stack opening, and the dielectric material is planarized. Additional methods are disclosed, as well as semiconductor devices.

Semiconductor devices comprising steps

Methods of improving adhesion between a photoresist and conductive or insulating structures. The method comprises forming a slot through at least a portion of alternating conductive structures and insulating structures on a substrate. Portions of the conductive structures or of the insulating structures are removed to form recesses in the conductive structures or in the insulating structures. A photoresist is formed over the alternating conductive structures and insulating structures and within the slot. Methods of improving adhesion between a photoresist and a spin-on dielectric material are also disclosed, as well as methods of forming a staircase structure.

Methods of forming a staircase structure

Various embodiments disclosed relate to methods of manufacturing a textured surface comprising disposing a nanoparticulate ink on a substrate.

Patterning of nanostructures using imprint lithography

Some embodiments include an integrated assembly having a semiconductor die with memory array regions and one or more regions peripheral to the memory array regions. A stack of alternating insulative and conductive levels extends across the memory array regions and passes into at least one of the peripheral regions. The stack generates bending stresses on the die. At least one stress-moderating region extends through the stack and is configured to alleviate the bending stresses.

Integrated assemblies

An electronic device comprising at least one high aspect ratio feature in a base stack of materials, overlay marks in or on only an upper portion of the base stack of materials, and an additional stack of materials adjacent the base stack of materials, the additional stack of materials comprising the at least one high aspect ratio feature. Additional electronic devices and memory devices are disclosed, as are methods of forming high aspect ratio features in an electronic device.

Electronic devices comprising overlay marks, memory devices comprising overlay marks, and related methods

Methods of forming a semiconductor device

Methods of improving adhesion of photoresist in a staircase structure and methods of forming a staircase structure

Methods of forming staircase structures

Growing community of inventors

Boise, ID, United States of America

Rohit Kothari