International Business Machines Corporation

Apple Inc.

Lenovo (singapore) Pte. Ltd.

Rohan U Mandrekar

Daniel Mark Dreps

Tae Hong Kim

Jinwoo Choi

Matteo Cocchini

Tingdong Zhou

Zhaoqing Chen

Mahesh Bohra

Kevin Bills

Moises Cases

Roger Donell Weekly

Nusrat I Sherali

Douglas A Baska

John Lee Colbert

Paul Marian Harvey

Travis M Grigsby

Jun Zhai

Vidhya Ramachandran

Wei Xu

Mohamed Hassan Abu-Rahma

Sungjun Chun

Jacob Daniel Eisinger

Robert Bryant Chumbley

Shuai Jiang

Victor Zyuban

Chonghua Zhong

Per Hakan Hammarlund

Mengzhi Pang

Jamie L Langlinais

Lei Shan

Christopher M Laffoon

Alexander B Uan-Zo-li

Jaroslav Raszka

Dierk Kaller

Sambasivan Narayan

Long Huang

Sung J Kim

Robert O Bruckner

Hans L Yeager

Hong T Dang

Tae Tong Kim

A power delivery sub-system included in a computer system employs a primary voltage regulator circuit that generates a primary supply voltage on a primary power supply node. The power delivery sub-system also includes multiple bypass voltage regulator circuits that source corresponding bypass currents to a local power supply nodes in an integrated circuit. The integrated circuit includes multiple circuit blocks coupled to corresponding ones of the local power supply nodes, and multiple local voltage regulator circuits coupled to the primary power supply node. When a voltage level of a given local power supply node drops below a threshold value, a corresponding local voltage regulator circuit sources a supply current to the given local power supply node.

Merged power delivery

Some embodiments of the inventive subject matter are directed to forming, on a first circuit board, first pins that connect to first leads of a first electronic component; forming, on the first circuit board, second pins that connect to second leads of a second electronic component; affixing the first circuit board to a second circuit board having a first layer with first wires; and forming second wires on a second layer of the second circuit board, wherein said forming the second wires creates an electrical connection on the second circuit board between a portion of the first pins and a portion of the second pins. In some embodiments, the second circuit board is smaller than the first circuit board, and the second layer of the second circuit board is, in length, approximately equivalent to a distance between the first electronic component and the second electronic component.

Implementing high-speed signaling via dedicated printed circuit-board media

Integrated passive devices (IPDs), electronic packaging structures, and methods of testing IPDs are described. In an embodiment, an electronic package structure includes an IPD with an array of capacitor banks that are electrically separate in the IPD, and a package routing that includes an interconnect electrically connected to an IC and a plurality of the capacitor banks in parallel.

Trimmable banked capacitor

An electronic device including a plurality of interconnects are orthogonally arranged in a grid pattern and evenly spaced by a first distance, the plurality of interconnects include: a first conductor pair with conductors arranged next to each other in a first direction, the first direction is oriented diagonally relative to the orthogonal grid pattern, a second conductor pair with conductors arranged next to each other in a second direction substantially perpendicular to the first direction, each conductor of the second conductor pair is spaced by the first distance from each signal conductor of the first conductor pair, and a third conductor pair with conductors arranged next to each other in a third direction substantially parallel to the first direction, each conductors of the third conductor pair is spaced by the first distance from one of the signal elements of the second conductor pair.

Interconnect array pattern with a 3:1 signal-to-ground ratio

A multi layer interconnecting substrate has at least two spaced apart metal layers with a conductive pad on each one of the metal layers. Two different types of insulating layers are placed between the metal layers. The placement is such that one of the two different types of insulating layers is placed between the conductive pads and the other type of insulating layer is placed between the two spaced apart metal layers.

Coreless multi-layer circuit substrate with minimized pad capacitance

One aspect is a method that includes identifying, by a power via placement tool executing on a processor of a circuit design system, a source and a sink of a voltage domain of a multi-layer circuit board based on a design file defining a layout of the multi-layer circuit board. A number of power vias to support a maximum current demand from the source to the sink is determined. Positions of a plurality of the power vias are determined at locations of the multi-layer circuit board forming paths through the power vias between the source and the sink and having a substantially equal total path length through each total path defined between the source and the sink through at least one of the power vias. The design file is modified to include the power vias at the positions.

Distribution of power vias in a multi-layer circuit board

A mechanism is provided for packaging a multiple socket, one-hop symmetric multiprocessor topology. The mechanism connects each of a first plurality of processor modules to a first multiple-socket planar via a respective one of a first plurality of land grid array (LGA) connectors. The mechanism connects the first multiple-socket planar to a first side of a redistribution card via a second plurality of LGA connectors. The mechanism connects each of a second plurality of processor modules to a second multiple-socket planar via a respective one of a third plurality of LGA connectors. The mechanism connects the second multiple-socket planar to a second side of the redistribution card via a fourth plurality of LGA connectors.

Packaging for eight-socket one-hop SMP topology

Example multi-layer printed circuit boards ('PCBs') are described as well as methods of manufacturing a PCB. Embodiments include depositing upon layers of laminate printed circuit traces and joining the layers of laminate. Embodiments also include drilling at least one via hole through the layers of laminate and placing in the via hole a via conductor comprising a used portion and an unused portion, the via conductor comprising copper coated with a second metal having a conductivity lower than the conductivity of copper.

Through-hole-vias in multi-layer printed circuit boards

The embodiments of the present invention relate generally to the fabrication of integrated circuits, and more particularly to a structure and method for fabricating differential wiring patterns in multilayer glass-ceramic (MLC) modules. A structure and method of forming a MLC having layers with staggered, or offset, pairs of lines formed directly on one another are disclosed. In addition, a structure and method of forming a MLC having layers with staggered, or offset, pairs of lines that periodically reverse polarity are disclosed.

High speed differential wiring in glass ceramic MCMS

Growing community of inventors

Austin, TX, United States of America

Rohan U Mandrekar