Apple Inc.

Rohan Sanjeev Patil

Tatsuya Iwamoto

Kutty Banerjee

Gokhan Avkarogullari

Jason P Jane

Pratik Chandresh Shah

Subodh Asthana

Kyle J Haughey

Systems, methods, and computer readable media to manage power for a graphics processor are described. When the power management component determines the graphics processor is idle when processing a current frame by the graphics processor, the power management component predicts an idle period for the graphics processor based on the work history. The power management component obtains a first latency value indicative of a power on time period and a second latency value indicative of a power off time period for a graphics processor component, such as graphics processor hardware. The power management component provides power instructions to transition the graphics processor component to the power off state based on a determination that a combined latency value of the first latency value and the second latency value is less than the idle period.

Proactive power management of a graphics processor

Systems, methods, and computer readable media to improve task switching operations in a graphics processing unit (GPU) are described. As disclosed herein, the clock rate (and voltages) of a GPU's operating environment may be altered so that a low priority task may be rapidly run to a task switch boundary (or completion) so that a higher priority task may begin execution. In some embodiments, only the GPU's operating clock (and voltage) is increased during the task switch operation. In other embodiments, the clock rate (voltages) of supporting components may also be increased. For example, the operating clock for the GPU's supporting memory, memory controller or memory fabric may also be increased. Once the lower priority task has been swapped out, one or more of the clocks (and voltages) increased during the switch operation could be subsequently decreased, though not necessarily to their pre-switch rates.

Fast GPU context switch

One disclosed embodiment includes a method of scheduling graphics commands for processing. A plurality of micro-commands is generated based on one or more graphics commands obtained from a central processing unit. The dependency between the one or more graphics commands is then determined and an execution graph is generated based on the determined dependency. Each micro-command in the execution graph is connected by an edge to the other micro-commands that it depends on. A wait count is defined for each micro-command of the execution graph, where the wait count indicates the number of micro-commands that the each particular micro-command depends on. One or more micro-commands with a wait count of zero are transmitted to a ready queue for processing.

Low latency firmware command selection using a directed acyclic graph

One disclosed embodiment includes a method of graphics processing. The method includes receiving an indication to update a current frame on a display. A plurality of graphics command are determined to be associated with a next frame that replaces the current frame. A power-up command is generated based on the received indication, configured to cause GPU hardware to begin an initialization operation. The central processing unit processes the plurality of graphics command. Prior to completely process the plurality of graphics command, a power-up command is sent to a GPU firmware. The GPU firmware initializes the GPU hardware based on the power-up command. The processed plurality of graphics command is also transmitted to the GPU hardware. The GPU hardware executes the processed plurality of graphics command to render the next frame on the display.

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San Francisco, CA, United States of America

Rohan Sanjeev Patil