Apple Inc.

Intel Corporation

Roger W Van Brunt

Florin Alexandru Oprescu

Andrew M Volk

Daniel L Hillman

Michael D Teener

Terry L Baucom

Christopher Nilson

A bus circuit for implementing a high speed dominant logic bus for a differential signal. The bus circuit is useful in a communication network having a plurality of multi-port nodes that are coupled by point-to-point links that communicate differential signals. Each port in the node includes a bus driver that receives the differential signal received at the port. The bus driver supplies a differential current signal to a first bus. A terminator circuit is coupled to the first differential bus, to receive the differential current signals supplied from the ports. The terminator circuit, responsive to the differential current signal, outputs a differential voltage signal indicative of either a dominant state or a non-dominant state to a second differential bus, which is coupled to the plurality of ports for transmission. A biasing circuit for the bus drivers allows operation at low voltages, and furthermore insures the zero crossing of the differential voltage signal on the second differential bus.

High-speed dominant mode bus for differential signals

A CMOS differential twisted-pair driver which utilizes CMOS switches and current sources advantageously. No alternative power supply is required, the switches do not have to be low impedance and the device is low power. The preferred embodiment driver further limits signal overshoot and common mode energy. The signal transmission facility is bi-directional so an off state is provided. It is doubly terminated to provide for symmetry, improved bandwidth and reduces reflective signal noise. The double termination also provides for faster rise and fall times which reduces the systems sensitivity to receiver offset.

CMOS differential twisted-pair driver

The delay line separator extracts a clock signal from a combined data/clock encoded signal received over a serial data bus, despite the presence of significant duty cycle distortion. Such distortion affects the width of symbols within received data packets but does not affect the timing between successive rising edges within the received pulse string. To extract the chock signal from the distorted signal, the separator exploits a pre-filter circuit which generates 2 -nanosecond pulses synchronized with each rising edge in the received signal. A 20-nanosecond pulse train is transmitted down a delay line having twelve delay elements. Circuits are connected to every other delay element within the delay line for generating 10-nanosecond pulses, synchronized with each rising edge of the pulse train. Outputs from the circuits are combined using an OR gate to yield a 10-nanosecond clock signal. The pre-filter generates 20-nanosecond pulses, rather than 10-nanosecond pulses, to ensure that the pulses successfully propagate the entire length of the delay line, despite the presence of significant dispersion within each delay element. Additional circuits are tapped into the delay elements, as desired, to generate additional clock signals delayed by 5- or 10-nanosecond intervals.

Delay line separator for data bus

A differential-to-CMOS level signal converter which receives a first differential signal having a small amplitude difference between the binary signals. The differential-to-CMOS level converter amplifies and level shifts the binary differential signal and outputs a single-ended CMOS level signal suitable for use by digital CMOS logic. A circuit for biasing the differential-to-CMOS level converter is coupled to the level shifting circuitry.

Differential to single-ended CMOS converter

In a driver circuit for a twisted pair cable, a compensator for preventing appreciable common mode current flow into or out of the twisted pair cable in response to the device receiving a wide range of common mode voltage bias levels. A wide range of external bias voltages may be received as a result of variations in the ground node voltages of two coupled devices. The compensator circuit utilizes a feed back loop and monitors the bias voltage received on the twisted pair cable. As the magnitude of the common mode current increases due to external bias voltage variation from a reference bias voltage, the current flow of p-channel transistors, coupled in an arrangement of the present invention, is increased (or decreased, as necessary) so that reduced common mode current flows onto the twisted pair cable. The present invention reduces appreciable common mode current flow through the twisted pair cable from the driver that are due to variations in the external bias voltage between communication devices. The present invention provides high common mode output impedance for the driver circuit by altering the effective common mode common mode early voltage characteristics of the driver circuit while utilizing shorter channel length transistors for high speed communication capacity. The present invention also offers reduced current supply capacity of the common mode bias voltage source. The present invention operates ideally within driver circuits compatible with the IEEE P1394 communication standard.

Common mode early voltage compensation subcircuit for current driver

A node for a communication system that has a plurality of nodes, each of which may be coupled to a local host. The nodes are coupled between themselves in a tree topology by a plurality of point-to-point links. The interconnected nodes provide a first bus configuration for arbitration like a single bus. Following arbitration, the interconnected nodes provide a second configuration for high speed unidirectional data transfer without the bandwidth limitations of a single bus. Each node includes an arbiter, a data bus, a plurality of ports, a first multiplexer to select either the arbiter or the data bus, and a second multiplexer to select either the arbiter or the data bus. The data bus includes a transmit bus and a receive bus that are coupled with a repeater circuit that can resynchronize the data. During arbitration, the multiplexers select the arbiter to provide the function of a single bus for all the nodes. During data transfer, the multiplexers are configured for transmission of data. Furthermore, a node can function as a repeater and resynchronizer even if it is not connected to a local host or if the local host is turned off or otherwise nonoperational.

Communication node with a first bus configuration for arbitration and a

In a computer bus arrangement in which a plurality of nodes are interconnected by communication links, control signals are exchanged between the nodes concerning the transmission rate of a data message to be transmitted and the reception rate capability of the nodes. The data message is passed to those nodes which have a reception rate capability which matches or exceeds the transmission rate associated with the message. The other nodes receive a mock data message at a rate within their capability. In order to aid in synchronization within the bus arrangement, the duration of the mock data message is the same as the data message received by the other nodes, even though they are transmitted at different rates.

Method and apparatus for a dynamic, multi-speed bus architecture in

The class AB amplifier is configured to provide low quiescent current while achieving high internal switching rates. The buffer is connected to a large external capacitance which provides external compensation. The amplifier includes an input stage which converts differential voltages to current. An output stage provides an output current and also provides a feedback current into the input stage. A biasing network provides voltage for biasing various nodes within the amplifier. Cross-coupling is provided within the output stage for achieving a low quiescent current. A pair of current limiting circuits, one for p-channel element and another for n-channel elements, is also provided.

CMOS class AB amplifier for driving capacitive and resistive loads

A bus circuit for implementing a high speed dominant logic bus for a differential signal. The bus circuit is useful in a communication network having a plurality of multi-port nodes that are coupled by point-to-point links that communicate differential signals. Each port in the node includes a bus driver that receives the differential signal received at the port. The bus driver supplies a differential current signal to a first bus. A terminator circuit is coupled to the first differential bus, to receive the differential current signals supplied from the ports. The terminator circuit, responsive to the differential current signal, outputs a differential voltage signal indicative of either a dominant state or a non-dominant state to a second differential bus, which is coupled to the plurality of ports for transmission. A biasing circuit for the bus drivers allows operation at low voltages, and furthermore insures that the zero crossing of crossing of the differential voltage signal on the second differential bus.

High speed dominant mode bus for differential signals

A bus interconnect device including port control logic for a communication network having a plurality of multi-port nodes that are connected with point-to-point links. Each node includes a transceiver, turn around logic that controls the transceiver, and a dominant logic physical bus that is coupled to all ports in a node. A bus interconnect device includes a first port, a second port, and a point-to-point link between the first and second ports. During arbitration, from the viewpoint of each node, the bus interconnect devices cause the plurality of physical buses to appear to be a single logical bus having a dominant logic. During data transfer following arbitration, the bus interconnect devices are configured to transmit data from the winning node to all other nodes.

Bus interconnect circuit including port control logic for a multiple

A mechanism and method for efficiently communicating information regarding particular communication rate ('speed signal') between two or more communication stations (of a communication network). The transmitter operates on the IEEE P1394 High Performance Serial Bus to supply both differential and common mode signaling required by the IEEE standard for exemplary data transfer rates of 100 and 200 Mbit transmission. The present invention includes a transmission circuit that may operate in a differential signal mode and simultaneously in a common mode signal mode both utilizing a twisted pair cable. Data may be transmitted on the twisted pair at small differential signals. Information regarding the signal speed between two coupled units may be simultaneously transmitted using variations in the common mode voltage over the twisted pair. Communication may be initiated at a slower communication rate and then upgraded as appropriate for the two units. The present invention allows an efficient single circuit mechanism for communication units to transmit differential data and also to signal the use of a high speed communication rate with a common mode voltage. The present invention is especially useful within networks having units of varying versions and signal transfer rates.

Circuit and method for twisted pair current source driver

The de-skewer utilizes a delay line to generate a set of delayed versions of an input clock signal. A bank of flip-flops compares pulses within the delayed clock signals to a synchronization pulse provided within an input data signal. A detector receives outputs from the flip-flops and selects the delayed clock signal having the least amount of skew based on the values of the output from the flip-flops. A multiplexer outputs the selected delayed clock. The de-skewer provides a simple, open-loop circuit for eliminating skew between parallel transmission paths. The de-skewer is ideally suited for eliminating skew from sources which do not vary significantly as a function of time. In particular, the de-skewer is well-suited for use in a data transmission system providing short bursts of high data rate transmissions. A double-edged de-skewer is also described which is capable of generating a pair of clock signals for use in eliminating duty cycle distortion.

Adaptive clock skew and duty cycle compensation for a serial data bus

The level shifter provides a selective voltage level shift to a common mode signal level on a twisted pair signal line. The level shift is selectively performed based upon the input level of the common mode voltage. The level shifter is advantageously employed in a low voltage circuit wherein lacking sufficient voltage head room to accommodate a constant common mode level shift. An exemplary embodiment is described wherein the level shifter is employed within a bus transceiver of a bus system employing IEEE P1394 bus protocol. In the exemplary embodiment, the selective level shift is applied only to bus signals occurring during an idle phase and an arbitration phase, with no level shift performed during a data phase.

Method and apparatus for implementing a common mode level shift in a bus

An adaptive data separator for detecting systematic differences between the arrivals of the rising and falling edges of a digital signal and for compensating for the difference. Data packets from a transmission source are prefixed with two data bits of known values. The data separator is also supplied with four clock signals per bit, one corresponding to an ideal rising edge and three following every 5 nanoseconds. The two prefix bits preceding a data packet are then sampled at each of the clock signals. Since all information in a given data packet undergoes the same systematic distortion, the logic of the adaptive data separator can determine the optimum clock signal to use in sampling each bit of data for the packet. Through several multiplexers the incoming data is then clocked to the optimal clock signal for sampling.

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San Francisco, CA, United States of America

Roger W Van Brunt