International Business Machines Corporation

Macronix International Co., Ltd.

Qimonda North America Corporation

Roger W Cheek

Chung H Lam

Matthew Joseph Breitwisch

Alejandro Gabriel Schrott

Eric Andrew Joseph

Bipin Rajendran

Yu Zhu

Hsiang-Lan Lung

Ming-Hsiu Lee

Luis Alfonso Lastras-Montano

Jeffrey Bowman Johnson

Thomas Mittelholzer

John Peter Karidis

Michele M Franceschini

Matthew Joseph BrightSky

Michael Joseph Zierak

Gerhard Ingmar Meijer

Ibrahim M Elfadel

Mayank Sharma

Stefanie Ruth Chiras

Beth Ann Rainey

John Edward Cronin

Dharmendra S Modha

Arne Watson Ballantine

Ying Di Zhang

Chao-I Wu

David William Abraham

Yen-Hao Shih

Stephen Mark Rossnagel

Thomas Nirschl

William Joseph Murphy

Robert Michael Geffken

Mark C Lamorey

Matthew J Rutten

Matthew D Moon

Douglas P Nadeau

Terrance M Wright

Michael B Rice

George A Dunbar, Iii

Douglas S Armbrust

Prabhat Tiwari

Doreen D DiMilia

Mark L Reath

John M Baker

David H Yao

A memory cell and a method of making the same, that includes insulating material deposited on a substrate, a bottom electrode formed within the insulating material, a plurality of insulating layers deposited above the bottom electrode and at least one of which acts as an intermediate insulating layer. A via is defined in the insulating layers above the intermediate insulating layer. A channel is created for etch with a sacrificial spacer. A pore is defined in the intermediate insulating layer. All insulating layers above the intermediate insulating layer are removed, and the entirety of the remaining pore is filled with phase change material. An upper electrode is formed above the phase change material.

Uniform critical dimension size pore for PCRAM application

A material can be locally etched with arbitrary changes in the direction of the etch. A ferromagnetic-material-including catalytic particle is employed to etch the material. A wet etch chemical or a plasma condition can be employed in conjunction with the ferromagnetic-material-including catalytic particle to etch a material through a catalytic reaction between the catalytic particle and the material. During a catalytic etch process, a magnetic field is applied to the ferromagnetic-material-including catalytic particle to direct the movement of the particle to any direction, which is chosen so as to form a contiguous cavity having at least two cavity portions having different directions. The direction of the magnetic field can be controlled so as to form the contiguous cavity in a preplanned pattern, and each segment of the contiguous cavity can extend along an arbitrary direction.

Catalytic etch with magnetic direction control

Systems, methods, and devices for iteratively writing contents to memory locations are provided. A statistical model is used to determine a sequence of pulses to write desired contents to a memory location. The contents can be expressed as a resistance value in a range to store one or more bits in a memory cell. For phase change memory, an adaptive reset pulse and one or more annealing pulses are selected based on a desired resistance range. Reading the resistance value of the memory cell can provide feedback to determine adjustments in an overall pulse application strategy. The statistical model and a look up table can be used to select and modify pulses. Adaptively updating the statistical model and look up table may reduce the number of looping iterations to shift the resistance value of the memory cell into the desired resistance range.

Memory programming for a phase change memory cell

Memory cell structures for phase change memory. An example memory cell structure comprising includes a bottom electrode comprised of electrically conducting material, and phase change material disposed above the bottom electrode. A layer of thermally insulating material is disposed, at least partially, between the bottom electrode and the phase change material. The thermally insulating material is comprised of Tantalum Oxide. A top electrode is comprised of electrically conducting material.

Thermally insulated phase change material cells

A memory chip and methods of fabricating a memory device with different programming performance and retention characteristics on a single wafer. One method includes depositing a first bounded area of phase change material on the wafer and depositing a second bounded area of phase change material on the wafer. The method includes modifying the chemical composition of a switching volume of the first bounded area of phase change material. The method includes forming a first memory cell in the first bounded area of phase change material with a modified switching volume of phase change material and a second memory cell in the second bounded area of phase change material with an unmodified switching volume of phase change material such that the first memory cell has a first retention property and the second memory cell has a second retention property. The first retention property is different from the second retention property.

Approach for phase change memory cells targeting different device specifications

A prompt-shift device having reduced programming time in the sub-millisecond range is provided. The prompt-shift device includes an altered extension region located within said semiconductor substrate and on at least one side of the patterned gate region, and an altered halo region located within the semiconductor substrate and on at least one side of the patterned gate region. The altered extension region has an extension ion dopant concentration of less than about 1E20 atoms/cm, and the altered extension region has a halo ion dopant concentration of greater than about 5E18 atoms/cm. The altered halo region is in direct contact with the altered extension region.

Method to tailor location of peak electric field directly underneath an extension spacer for enhanced programmability of a prompt-shift device

A method of manufacturing an electrode is provided that includes providing a pillar of a first phase change material atop a conductive structure of a dielectric layer; or the inverted structure; forming an insulating material atop dielectric layer and adjacent the pillar, wherein an upper surface of the first insulating material is coplanar with an upper surface of the pillar; recessing the upper surface of the pillar below the upper surface of the insulating material to provide a recessed cavity; and forming a second phase change material atop the recessed cavity and the upper surface of the insulating material, wherein the second phase change material has a greater phase resistivity than the first phase change material.

Pore phase change material cell fabricated from recessed pillar

A method for fabricating a phase change memory device including a plurality of in via phase change memory cells includes forming pillar heaters formed of a conductive material along a contact surface of a substrate corresponding to each of an array of conductive contacts to be connected to access circuitry, forming a dielectric layer along exposed areas of the substrate surrounding the pillar heaters, forming an interlevel dielectric (ILD) layer above the dielectric layer, etching a via to the dielectric layer, each via corresponding to each of pillar heater such that an upper surface of each pillar heater is exposed within each via, recessing each pillar heater, depositing phase change material in each via on each recessed pillar heater, recessing the phase change material within each via, and forming a top electrode within the via on the phase change material.

In via formed phase change memory cell with recessed pillar heater

A memory cell structure and method for forming the same. The method includes forming a pore within a dielectric layer. The pore is formed over the center of an electrically conducting bottom electrode. The method includes depositing a thermally insulating layer along at least one sidewall of the pore. The thermally insulating layer isolates heat from phase change current to the volume of the pore. In one embodiment phase change material is deposited within the pore and the volume of the thermally insulating layer. In another embodiment a pore electrode is formed within the pore and the volume of the thermally insulating layer, with the phase change material being deposited above the pore electrode. The method also includes forming an electrically conducting top electrode above the phase change material.

Thermally insulated phase change material memory cells

Thermally insulated phase material cells

A system, method and computer program product for producing spike-dependent plasticity in an artificial synapse is disclosed. According to one embodiment, a method for producing spike-dependent plasticity in an artificial neuron comprises generating a pre-synaptic spiking event in a first neuron when a total integrated input to the first neuron exceeds a first predetermined threshold. A post-synaptic spiking event is generated in a second neuron when a total integrated input to the second neuron exceeds a second predetermined threshold. After the pre-synaptic spiking event, a first pulse is applied to a pre-synaptic node of a synapse having a phase change memory element. After the post-synaptic spiking event, a second varying pulse is applied to a post-synaptic node of the synapse, wherein current through the synapse is a function of the state of the second varying pulse at the time of the first pulse.

System for electronic learning synapse with spike-timing dependent plasticity using phase change memory

The invention provides a method to enhance the programmability of a prompt-shift device, which reduces the programming time to sub-millisecond times, by altering the extension and halo implants, instead of simply omitting the same from one side of the device as is the case in the prior art prompt-shift devices. The invention includes an embodiment in which no additional masks are employed, or one additional mask is employed. The altered extension implant is performed at a reduced ion dose as compared to a conventional extension implant process, while the altered halo implant is performed at a higher ion dose than a conventional halo implant. The altered halo/extension implant shifts the peak of the electrical field to under an extension dielectric spacer.

Phase change memory devices and methods for operating described herein are based on the discovery that, following an initial high current operation applied to a phase change memory cell to establish the high resistance reset state, the current-voltage (I-V) behavior of the memory cell under different bias voltages can be used to detect if the memory cell is a defect cell having poor data retention characteristics.

Methods and apparatus for reducing defect bits in phase change memory

Thermally insulated phase change material memory cells with pillar structure

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Somers, NY, United States of America

Roger W Cheek