Taiwan Semiconductor Manufacturing Comp. Ltd.

Roger Tai

Chii-Horng Li

Yen-Ru Lee

Hsueh-Chang Sung

Pei-Ren Jeng

Yih-Ann Lin

Chien-Wei Lee

Heng-Wen Ting

Chih-Shan Chen

Tzu-Hsiang Hsu

Tzu-Ching Lin

Yan-Ting Lin

Chih-Yun Chin

Davie Liu

An embodiment is a semiconductor structure. The semiconductor structure includes a substrate. A fin is on the substrate. The fin includes silicon germanium. An interfacial layer is over the fin. The interfacial layer has a thickness in a range from greater than 0 nm to about 4 nm. A source/drain region is over the interfacial layer. The source/drain region includes silicon germanium.

Interfacial layer between fin and source/drain region

Interfacial layer between Fin and source/drain region

A semiconductor device includes a semiconductor base. A dielectric isolation structure is formed in the semiconductor base. A source/drain of a FinFET transistor is formed on the semiconductor base. A bottom segment of the source/drain is embedded into the semiconductor base. The bottom segment of the source/drain has a V-shaped cross-sectional profile. The bottom segment of the source/drain is separated from the dielectric isolation structure by portions of the semiconductor base.

V-shape recess profile for embedded source/drain epitaxy

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Tainan, Taiwan

Roger Tai