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L-3 Communications Corporation

Roger T Baker

Vaughn Lee Mower

Merle LeRoy Keller, Jr

The invention relates to a modular pod mattress used for sleeping. The mattress includes a structural frame having bottom rails, guide rails and a dividing rail. A plurality of modular pods are secured to the frame to form the customized mattress that relates directly to the height and eight distribution of an individual's body parts to provide the maximum quality sleep environment unique to that individual. The modular pods include a plurality of spring members, which may have varying elasticity or resistant levels. The modular pods are supported by a support platform that prevents the pods from sagging or deflecting during use of the mattress. A horizontal scale system may be utilized to determine the specific weight of a particular body part, e.g., head, shoulders, thorax, buttocks, thighs, calves and feet, of the user.

Modular pod mattress

A modular pod mattress with an integral mattress subsurface platform rail system, a plurality of modular pods to be securely fitted into the mattress subsurface platform rail system, a first compartment to house a mattress lining, and a second compartment to house a mattress topper. The mattress subsurface platform rail system comprises a plurality of rails for forming a series of track mounting spaces for receiving and securing the plurality of modular pods. Each modular pod consists of a plurality of coils springs with varying elasticity that is dependent on the user's height and weight distribution. The modular pods may be removed and replaced pod by pod once worn as opposed to replacing the entire mattress.

Systems and methods for improving the reliability of a hub-spoke communications system use a first antenna and a second antenna at the hub terminal. Spread spectrum transmission from the hub terminal uses the first antenna, and the second antenna is enabled when blockage between the first antenna and any one of the spoke terminals is present. The first antenna and the second antenna have substantially orthogonal polarizations. The spread spectrum transmissions from the first antenna and second antenna have different pseudonoise code timing so that the received transmissions are offset by at least one chip interval from each other.

Communications reliability in a hub-spoke communications system

A dynamic memory cell with automatic refreshing is described which requires only three insulated gate field effect transistors (IGFETs). Binary datum is stored in the cell by maintaining the gate of the first IGFET high for a one and low for a zero. The second IFGET is used for cell selection in the read and write operations, and is in series with the first transistor. The third IGFET has one gate electrode, but the channel region of this transistor has two regions, and the surface potential vs. gate voltage characteristics of these two regions differ. Regardless of the datum stored in the cell, pulsing the gate of this third transistor refreshes the memory cell.

Dynamic memory cell with automatic refreshing

A semiconductor random access memory is described in which the datum stored in one memory cell can be recalled without having to recall, temporarily store, and then re-enter the data stored in a column of memory cells. Datum can also be entered into one memory cell without having to recall and subsequently re-enter the data in a column of memory cells. During the recall and enter processes, only one of the normally off sense amps needs to be powered up. Compared to prior art one-transistor memories, this memory consumes less power and has a faster write cycle.

Three electrode dynamic semiconductor memory cell with coincident

In a semiconductor memory cell in which binary data is represented by the density of minority carriers stored in the inversion regions of two isolated MIS capacitors, a method of nondestructively recalling the datum stored therein is described. In this method, the minority carriers are extracted from either one or both of the inversion regions, and the resulting potential change across either one or both of the MIS capacitors is indicative of the datum stored in the memory cell. These memory cells can be used in random access memories with nondestructive recall and in content addressable memories.

Memory cell with nondestructive recall

A dynamic semiconductor memory cell which can be used in content addressable or associative memories is described. In the memory cell, a one is represented by storing a relatively large number of minority carriers in the potential well formed in a semiconducting substrate beneath a first storage electrode, and a zero is represented by storing a relatively large number of minority carriers in the potential well formed in a semiconducting substrate beneath a second storage electrode. The match zero operation is performed by extracting some of any of the minority carriers stored beneath the first storage electrode, which induces a relatively small potential change on that electrode if a zero is stored in the memory cell and induces a relatively large potential change on that electrode if a one is stored therein. Similarly, the match one operation is performed by interrogating the minority carriers stored in the potential well beneath the second storage electrode. In a memory, the storage electrodes of a plurality of memory cells are 'or' tied by connecting them in common.

Dynamic content addressable semiconductor memory

The memory cells in the rows of a random access memory are divided in to subrows, and an access transistor is used selectively isolate or connect the output terminals of each subrow of memory cells to the row line. When recalling the datum from a memory cell, the subrow is isolated, and thus the loading of the output signal from that memory cell is reduced. Consequently, an improved output signal can be obtained from a memory cell with a given size storage capacitance, or a smaller storage capacitance can be used in the memory cell, or both.

Circuit for the improvement of semiconductor memories

A method for representing, entering, storing, and recalling binary data from a semiconductor memory cell. Using this method, binary data is represented by the number of charge carriers stored in the two potential wells formed in a semiconducting material beneath two electrodes. The data so stored is read by opening a channel between these two potential wells, permitting carriers to flow between them, and detecting the resulting change in the potential of the two electrodes.

Method for operating charge transfer memory cells

A semiconductor device for the storage of binary data and means for electrically selecting a particular device from an array of such devices and either recalling the data stored therein, or introducing data to be stored therein, or both. The device includes two conducting electrodes in close proximity to each other and separated from a semiconducting material by a layer of electrically insulating material. Voltages of the correct polarity applied between the electrodes and the semiconductor induce depletion regions in the semiconductor. The device also includes a P-N junction in the semiconducting material in a region near one of the depletion regions. Binary data is entered in, maintained in, and recalled from the device by manipulating the voltages applied to the two electrodes, and controlling the voltage applied across the P-N junction.

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Mount Tabor, NJ, United States of America

Roger T Baker