International Business Machines Corporation

Agere Systems Inc.

Roger Ned Bailey

Bradley David McCredie

Robert L Mansfield

Alexander K Spencer

Michael P Taborn

Steven Michael Burchfiel

Michael Gerard Nealon

Hugh Rodney Stigdon

Ravi Kumar Arimilli

Michael Stephen Floyd

David Allen Brown

Kevin Franklin Reick

Timothy Michael Skergan

Johnny James LeBlanc

Jennifer Lane Vargus

A network processor or other type of processor includes an interface comprising a plurality of signal lines, and interface circuitry adapted to receive clock signals for respective interface clock domains of the processor. The interface circuitry comprises a plurality of sampling registers clocked by respective ones of the clock signals. The interface circuitry is configurable in a variety of different configurations, each providing a different association between designated subsets of the signal lines and the clock domains of the processor.

Processor with configurable association between interface signal lines and clock domains

A multi-chip apparatus is disclosed. In one form, the apparatus includes a carrier having a number of integrated circuit chips electrically coupled in a communications ring. The communications ring has carrier portions on the carrier and chip portions traversing the respective chips, permitting the communications ring carrier portions to be substantially straight, whereas at least one of the chip portions has a turn, enabling closure of the ring. In another aspect, the chips include respective regeneration circuitry interposed in the respective chip portions of the communications ring, for regenerating communications signals traversing the respective chips on the respective chip portions of the ring.

Multi-chip module having chips coupled in a ring

A method and system for testing an integrated circuit (IC) comprising a plurality of logic units and a plurality of level sensitive scan design latches (LSSD) chains (scan chains) where the partitioning of the scan chains is different than the partitioning of the logic units. Scan blocks, each scan block comprising multiplexers, a pseudo random pattern generator (PRPG), a partitioned multiple input shift register (MISR), functional logic and control function logic are distributively placed around and close to scan inputs and scan outputs of the IC in otherwise unused area too small for larger functional logic blocks. The MISR, which contains many loaded latches and other logic, would normally be the largest element of the scan block has been partitioned into a sub-set of a full MISR to minimize the size of an individual scan block. The scan block has the functionality to enable LSSD testing, system testing and logic built in self test (LBIST) by the way the individual scan blocks are wired to the scan inputs and scan outputs of the logic units within the IC. Two or more scan blocks are needed to make a complete MISR depending on the sub-set partitioning of the MISR in each scan block. Scan block may have particular IC scan inputs and scan outputs wired into many different multiplexer inputs maintaining a known testability so wiring at the local level may be optimized. Since most of the wiring to the logic unit scan chains, wiring to the central scan switch is minimized reducing wiring complexity and cost. By partitioning the MISR, the size of the standardized Scan blocks is minimized allowing the most effective placement around logic units.

Globally distributed scan blocks

The foregoing objects are achieved as is now described. A method and system for testing an integrated circuit are provided. A test substrate is provided which is manufactured by the same particular production technology for which the complex integrated circuit is designed. A pattern generator for generating test data and a result checker for comparing output data are embedded on the test substrate. Isolated portions of circuitry of the integrated circuit are selectively embedded onto the test substrate. The isolated portions of circuitry are subjected to testing by applying test data from the pattern generator to the isolated portions of circuitry. Errors in the isolated portions of circuitry are detected with the result checker by comparing data output from the isolated portions of circuitry with predetermined expected data, such that the integrated circuit is tested by susets, independently of testing the integrated circuit in its entirety.

Method and system for testing an integrated circuit

An integrated circuit chip has a first i/o set associated with a first edge of the chip and a second i/o set associated with a second edge of the chip. The first i/o set has a physical symmetry with respect to the second i/o set, to facilitate a number of the chips being interconnected in a ring to one another on a multi-chip module, with the chips symetrically disposed thereon. The chip has a bus interconnecting the first and second i/o sets for transmitting signals across the chip. The bus has regeneration circuitry for regenerating said signals traversing the chip.

Integrated circuit chip with features that facilitate a multi-chip module having a number of the chips

A floating point processing system and method of operation are disclosed. Single word precision denormalized operands and also misaligned operands are detected while such operands are being loaded into the first stage of a pipelined floating point unit. Such operands are aligned to a double word boundary and/or single word operands are normalized by a processing stages inserted into the pipe ahead of the first stage of the pipelined floating point unit thereby entering a one stage delay. In this way, misaligned operands and single word denormalized operands can be processed without the need for example to cancel the instruction, execute a normalize or alignment instruction and then re-launch the original instruction.

Variable stage load path and method of operation

An apparatus for detecting sticky and a leading one includes first circuitry capable of detecting both sticky and a leading one. The apparatus further includes second circuitry that determines whether a sticky or a leading one detect is required. Depending upon that determination, the second circuitry controls the first circuitry to perform a sticky detection or a leading one detection. A method practiced by the apparatus includes the steps of detecting either sticky or a leading one utilizing the same circuitry, determining whether a sticky or a leading one detect is required, and controlling the circuitry in accordance with the determination of whether a sticky or a leading one detect is required.

Method and apparatus for sticky and leading one detection

A technique for use in an I/O channel to increase bus bandwidth during DMA data transfers between main system memory and a communication link is disclosed, including a pair of buffers, a plurality of counters adapted to selectively contain a count of data increments therein, and enhanced DMA control logic for monitoring buffer data content amount, and at a predetermined time during a given transfer initiating a bus arbitration so that it is completed simultaneously with the given transfer, thereby enabling the next data transfer from the buffer in use to immediately commence.

Look ahead bus transfer request

An interface circuit for providing an interface with the parallel data bus that transfers information in a multiple of formats. The interface includes a control circuit that receives or sends control signals from or to the parallel bus to regulate the data transfer and to specify one of the plurality of formats. An addressing circuit, connected to the control circuit, is provided for computing addresses for each of the data received or sent according to the specified format. An accessing circuit connected to the bus, control and address circuits is provided to store or retrieve data from or to the bus according to the computed data addresses. This interface provides a means to serialize data when, in one format, the first word of a data transfer is provided on one part of the data bus but, in a second format, the first data word is provided on another part of the data bus.

Multiple data format interface

A timer including a counter circuit that continuously provides an output of an iteratively increasing sequence of bits. The timer includes a timeout data circuit that forms a timeout data word from a specified time period and a first counter circuit output. A register is provided that stores the timeout data word at an address formed from a second counter circuit output. A comparison circuit is provided that compares each counter output with a timeout data word at the address formed from that counter output and provides a timeout signal when they are equal. This timer includes a constantly incrementing counter to address a register that includes a multiple of timeout condition specifications, and as a determination of when the timeout conditions stored in the register occur.

Growing community of inventors

Austin, TX, United States of America

Roger Ned Bailey