Texas Instruments Corporation

Other

Roger Mark Terry

Thomas J Aton

Robert L Pitts

Zhicheng Tang

Integrated circuit () includes substrate () with surface () and structure () including base levels (.(+1)), terminating cells (), and block () of standard cells arranged in rows (.(+1)), and another type of block () outside block (). Standard cells at at least two edges of block () have the following protections: (1) block () has strip of separation () having at least a minimum width from the edges of block (), and protected by one of the following: (2) terminating cells () reduce context effect and some terminating cells () are placed at at least one end of rows (.(+1)) of standard cells within first-named block (), and () the terminating cells () reduce context effect and some terminating cells () are at one end of a column of standard cells within block (). Other structures, devices, and processes are also disclosed.

Integrated circuits and processes for protection of standard cell performance from context effects

Integrated circuit () includes substrate () with surface () and structure () including base levels (.(+1)), terminating cells (), and block () of standard cells arranged in rows (.(+1)), and another type of block () outside block (). Standard cells at at least two edges of block () have the following protections: (1) block () has strip of separation () having at least a minimum width from the edges of block (), and protected by one of the following: (2) terminating cells () reduce context effect and some terminating cells () are placed at at least one end of rows (.(+1)) of standard cells within first-named block (), and (3) the terminating cells () reduce context effect and some terminating cells () are at one end of a column of standard cells within block (). Other structures, devices, and processes are also disclosed.

A method ( ) of determining a best focus for an integrated circuit stepper ( ). The method repeats various steps for a plurality of different focus levels. The repeated steps include forming a first element group (C ) on a wafer ( ), where the first element group comprises one or more elements and each of the one or more elements in the first element group has a shape. The repeated steps further include defining a first reference point (C ) for the first element group at a position relative to the shape of the one or more elements in the first element group. Similarly, the repeated steps include forming a second element group (C ) on the wafer, where the second group comprises one or more elements and each of the one or more elements in the second element group has a shape, and defining a second reference point (C ) for the second element group at a position relative to the shape of the one or more elements in the second element group. Still another repeated step is measuring a distance between the first reference point and the second reference point such that a distance measurement is identified for each of the plurality of different focus levels. Finally, the method selects as the best focus a focus level from the plurality of different focus levels and corresponding to a selected one of the distance measurements.

Integrated circuit system with automated best focus determination based on change in alignment due to predictable pattern degradation

A method and system of measuring misalignment between two levels wherein there is provided a first grating pattern (,) on a first layer (,) and a second grating pattern (,) on a second layer (41) capable of providing Moire fringes when disposed over the first grating pattern and which is disposed over the first grating pattern whereby the first and second grating patterns are capable of providing Moire fringes. Misalignment of the first layer relative to the second layer is measured from the position of the Moire fringe provided by the first and second grating patterns either visually or by optical instrumentation. The second layer is preferably transparent. The first grating pattern comprises a first group of plural sets of lines (,) , each of the lines of each of the sets being parallel to each other and extending across first imaginary straight lines, a second group of plural sets of lines (,) each of the lines of each set of lines of the second group being parallel to each other and each extending across a second imaginary straight line, each second imaginary line being parallel to a different one of the first imaginary lines, the second grating pattern being substantially identical to that of the first layer with the imaginary lines overlapping except that overlapping sets of lines are at an angle to each other different from being parallel and preferably overlap at an angle of less than about 60 degrees. Preferably, the first imaginary straight lines numbers four lines in the shape of a rectangle.

Moire overlay target

A dynamic fuse testing device includes an elongated handle, a head pivotally mounted to the handle, a fastener for tightening the head relative to the handle to place the head and handle at a desired angular position relative to one another, a pair of elongated electrically conductive test probes for contacting opposite ends of a fuse, a pair of mounting members attached in spaced relation to one another on the head, the mounting members having respective outer ends mounting the respective probes, one of the mounting members being stationarily mounted on the head and the other of the mounting member being rotatably mounted on the head such that its outer end is pivotally movable toward and away from the outer end of the one mounting member for adjusting the distance between the probes to accommodate fuses of different sizes, and a lamp and battery on the head connected in series with the probes such that the lamp is illuminated by contact of the probes with a properly functioning fuse.

Growing community of inventors

Allen, TX, United States of America

Roger Mark Terry