Inmos Limited

Roger M Shepherd

Michael David May

Richard J Gammack

Catherine Louise Barnaby

Anthony I Stansfield

Brian J Parson

Graham Stewart

A fully associative cache memory for virtual addressing comprises a data RAM (50), a first CAM cell array (51) for holding virtual page addresses which each require address translation to identify a physical page in a main memory, a second CAM cell array (52) holding line or word in page addresses which remain the same for virtual and physical addresses, a physical address memory (53) for holding physical page addresses for the main memory corresponding to virtual page addresses in said first array (51), said first array (51) being connected both to said physical address memory (52) to access said physical address memory in response to a hit output from said first CAM cell array and to control circuitry (57) coupled between said first and second arrays (51,52) and the data RAM (50) to access the data RAM (50) in response to hit outputs from both said first and second CAM cell arrays (51,52).

Cache memory system including a RAM for storing data and CAM cell arrays

A microcomputer has a processor arranged to share its time between a plurality of concurrent processes. Each process may have means (69) for indicating a time when the process may be executed. The processes may form a linked list of processes (T, U. V) awaiting scheduling for execution. A location (90) is provided for indicating the beginning of a timer list of processes awaiting execution and means (68) is provided for indicating the end of a timer list. The microcomputer may provide more than one timer list of processes of different priority. Each process may include a number of alternative components one or more of which is time dependent.

System for executing, scheduling, and selectively linking time dependent

A digital switch for selectively interconnecting a plurality of devices, including microcomputers, in a network comprises a plurality of inputs, a plurality of outputs and selectively operable interconnections which include decoding means for decoding data and acknowledgement bit packets, clock means, and means for generating under control of clock signals output bit packets having bit signals corresponding to bits of input bit packets.

Digital signal switch

Microcomputer with priority scheduling

Computer system with variable length process to process communication

Microcomputer

Growing community of inventors

Bristol, United Kingdom

Roger M Shepherd