Intel Corporation

Roger L Traylor

Ali S Oztaskin

Bill A Munson

Leonard W Cross

John L Allen

A method and apparatus for draining video data from a planarized video buffer in a video camera. The method includes the steps of reading a first sequence of video data from a first plane of the planarized image buffer starting at a buffer address indicated by a first pointer, and then reading a second sequence of video data from a second plane of the planarized image buffer starting at a buffer address indicated by a second read pointer. The apparatus includes an address generation unit and a sequence counter. The address generation unit includes a number of read pointers each configured to indicate a memory location within a different data plane of a video buffer. The address unit is configured to address a sequence of memory locations in a video buffer starting at a location indicated by an active one of the read pointers. The sequence counter is configured to detect when a final memory location of the sequence of memory locations has been addressed by the address generation unit and, in response, to select a different one of the read pointers to be the active read pointer.

Method and apparatus for draining video data from a planarized video

A method and apparatus for generating control signals for a high speed First In First Out (FIFO) buffer. Moreover, the present invention limits the instances where signal glitches may occur. A first pair of circular shift registers are used to control writing data to and reading data from the FIFO. The outputs of each register in each shift register are coupled to enable individual read and write lines of a FIFO memory device. A single logical one value circulates through the shift registers to indicate a FIFO location where data may be written to or from. Toggle latches are coupled to each shift register. The values in the toggle registers change responsive to a read or write operation. By comparing the logical one values in the corresponding positions in the shift registers, and considering the values from the toggle latches, EMPTY and FULL conditions are detected. Further, ALMOST EMPTY and ALMOST FULL signals are generated through a second pair of circular shift registers which shadow the operation of the first pair of circular shift registers. The second pair of circular shift registers is preset with one or more logical one values. By comparing the logical one values in the corresponding positions of the first and second pairs of shift registers, the ALMOST EMPTY and ALMOST FULL conditions are detected.

FIFO buffer with full/empty detection by comparing respective registers

A self-timed data pipeline comprised of a plurality of pipeline stages, each one incorporating at least one data latch coupled to selectively configured combinational logic is disclosed. The combinational logic is selectively configured to suit the demands of the particular data pipeline, and provides clocking to the at least one data latch in the pipeline stage. A self-timed data pipeline is thereby readily and inexpensively constructed with combinational logic and logic elements available in commodity application specific integrated circuits. The pipeline stages in the self-timed data pipeline advantageously communicate and pass data in an asynchronous fashion through the use of READY and ACKNOWLEDGE signals.

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Hillsboro, OR, United States of America

Roger L Traylor