Cypress Semiconductor Corporation

Longitude Flash Memory Solutions Ltd.

Netlogic Microsystems, Inc

Longitude Elash Memory Solutions Ltd

Roger J Bettman

Samuel Leshner

Iulian Constantin Gradinariu

Gary Peter Moscaluk

Vijay Raghavan

Cristinel Zonte

Vineet Argrawal

Anita X Meng

Donald Y Yu

S Babar Raza

Eric H Voelkel

Vineet Agrawal

Khaldoon S Abugharbieh

Donald A Krall

Andrew J Walker

Christopher W Jones

Barry Mark Loveridge

Sungkwon Lee

Christopher S Norris

Navaz M Lulla

Ramin Ighani

Bartosz Banachowicz

Fuad Badrieh

Sanjeev Kumar Maheshwari

Feng Dai

Sai Prashanth Dhanraj

Dung Ho

Leo F Luquette, Jr

Iman Rezanezhad Gatabi

Sing Y Wong

Systems and methods for driving a non-volatile memory device in a standby operating condition are disclosed. A standby detection circuit detects whether the non-volatile memory system is in a standby condition. In response to determining that the non-volatile memory system is in a standby condition, a bias control circuit provides bias currents to drivers of the non-volatile memory system in a standby mode.

Low standby power with fast turn on method for non-volatile memory devices

A method for driving a non-volatile memory system is disclosed. A standby detection circuit detects whether the nonvolatile memory system is in a standby condition. In response to determining that the non-volatile memory system is in a standby condition, a bias control circuit reduces bias currents provided to drivers of the non-volatile memory system in a standby mode. The non-volatile memory system is operated in the standby mode after the bias currents have been reduced, where an output signal indicating the standby mode is maintained until a read instruction is detected.

Low standby power with fast turn on for non-volatile memory devices

Disclosed herein are systems, methods, and devices for parallel read and write operations. Devices may include a first transmission device coupled to a local bit line and a global bit line associated with a memory unit of a memory array. The first transmission device may be configured to selectively couple the global bit line to the local bit line. The devices may further include a first device coupled to the local bit line and a sense amplifier. The first device may be configured to selectively couple the local bit line to the sense amplifier. The devices may also include a second device coupled to the local bit line and an electrical ground. The second device may be configured to selectively couple the local bit line to the electrical ground.

Systems, methods, and devices for parallel read and write operations

An ESD device that includes a gate and an n-drain region isolated from the gate and formed at least partially within an n-well region, which in turn is formed at least partially within a deep n-well region. The doping levels of the n-drain region, the n-well region and the deep n-well region are in a descending order. The ESD device has trigger and holding voltages, above the operation voltage of its protected circuit, which are layout-configurable by altering the distance between the n-drain and a side edge of the n-well region.

ESD clamp with a layout-alterable trigger voltage and a holding voltage above the supply voltage

A ternary content addressable memory (TCAM) cell () can include two memory elements (-and-) with a single bit line (-and-) per memory element. A TCAM cell () can also include a compare stack () and two word lines (and) that can connect to each memory element (-and-). The memory elements (-and-) can include SRAM type memory cells with one of two data terminals connected to a pre-write potential (Vpre, which can be a ground potential, or the like). Write operations can include pre-setting the data values of memory elements (-and-) to the pre-write potential prior to providing write data via the bit lines (-and-).

Content addressable memory (CAM) cell bit line architecture

In one embodiment, an electrically conductive trench in an integrated circuit allows for the formation of capacitors between the trench and other portions of the integrated circuit. For example, a capacitor may be formed between the trench and an electrically conductive line. Among other advantages, the capacitor provides a relatively large capacitance while occupying a relatively small area.

Trench-based capacitor for integrated circuits

An integrated circuit including a first cell configured to perform boundary scan testing, and an I/O node coupled to the first cell, wherein the I/O node is configured to carry a first differential signal. A level translator may be coupled between the I/O node and the first cell, wherein the level translator is configured to translate the first differential signal into a single ended signal. A level translator may be coupled between the I/O node and the first cell, wherein the level translator is configured to translate a single ended signal into the first differential signal. Core logic may be coupled to the first cell, wherein the core logic is configured to process a second differential signal, and a level translator may be coupled between the core logic and the first cell, wherein the level translator is configured to translate the second differential signal into a single ended signal.

Boundary scan register for differential chip core

An input gate protection circuit has a pass transistor having a source coupled to an input signal. A first voltage range control circuit is coupled to a gate of the pass transistor. A second voltage range is control circuit coupled to the gate of the pass transistor.

Input gate protection circuit and method

A programmable logic device comprising one or more macrocells and a product term array. The macrocells may comprise logic that may be configured to (i) generate and propagate a carry signal and (ii) generate a sum bit. The product term array may comprise two product terms per macrocell.

Reduced product term carry chain

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Los Altos, CA, United States of America

Roger J Bettman